NXP Semiconductors LPC11U67JBD100E

Overview

LPC11U67JBD100E from NXP Semiconductors is a 32-bit ARM Cortex-M0+ microcontroller operating at up to 50 MHz, featuring 128 KB flash, 20 KB SRAM, and 4 KB EEPROM. It integrates USB 2.0 full-speed device controller with on-chip PHY, five USARTs (including RS-485 mode), two I²C interfaces (one Fast-mode Plus), and a 12-bit ADC with 12 input channels-targeted for embedded control in GPS trackers and medical monitors.

For engineers reviewing the LPC11U67JBD100E datasheet, LPC11U67JBD100E pinout, LPC11U67JBD100E application, or LPC11U67JBD100E equivalent, key selection criteria include its LQFP100 package with 80 GPIO pins, dual PLL architecture (system + USB), RTC with VBAT support, and hardware CRC engine for firmware integrity verification.

Technical Context

The LPC11U67JBD100E implements an ARM Cortex-M0+ core with a two-stage pipeline, NVIC, Micro Trace Buffer (MTB), and Serial Wire Debug (SWD) interface. Its memory subsystem includes 128 KB flash with page erase, 20 KB SRAM (comprising one 16 KB block and two 2 KB blocks), and 4 KB EEPROM supporting IAP/ISP.

Peripherals are organized via an AHB multilayer matrix, enabling concurrent DMA transfers from UART, SSP, I²C, ADC, and SCTimer/PWM modules. The clock system uses a 12 MHz internal RC oscillator (±1 %), programmable watchdog oscillator (9.4 kHz–2.3 MHz), crystal oscillator (1–25 MHz), and two dedicated PLLs-one for CPU and one for USB-ensuring precise timing without external high-frequency crystals.

Key Specifications

Pinout & Package

LPC11U67JBD100E is housed in a plastic LQFP100 package (14 mm × 14 mm × 1.4 mm, SOT407-1), with 100 leads and exposed thermal pad. Pin functions are software-configurable via IOCON registers; all GPIO pins support pull-up/pull-down, open-drain, glitch filtering, and digital filtering.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microcontroller applications.

Compared with LPC11U68JBD100, the LPC11U67JBD100E offers identical peripheral integration and package but reduced memory-making it optimal for cost-sensitive, fixed-function applications. Versus LPC1343FBD48, it delivers USB-native capability and EEPROM at lower power, though with less raw compute throughput.

Availability

LPC11U67JBD100E is available at Aetrix Electronics and suitable for GPS trackers, medical monitors, car radio head units, and three-phase e-meters requiring stable component supply, long-term lifecycle assurance, and industrial-grade temperature performance.

Supply support for LPC11U67JBD100E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.

The LPC11U6x product line was designed for ultra-low-cost, USB-enabled embedded control applications demanding high integration, robust power management, and certified USB device compliance-targeting portable and battery-operated systems.

FAQ

What is the maximum operating frequency of the LPC11U67JBD100E?

The LPC11U67JBD100E operates at a maximum CPU frequency of 50 MHz using its ARM Cortex-M0+ core. This speed is achieved via the system PLL driven by either the internal 12 MHz RC oscillator (trimmed to ±1 % accuracy) or an external crystal (1–25 MHz). The core supports single-cycle I/O access, ensuring deterministic peripheral response at full clock rate. The LPC11U67JBD100E maintains this performance across its full −40 °C to +105 °C operating temperature range.

Does the LPC11U67JBD100E support USB device functionality without an external crystal?

Yes, the LPC11U67JBD100E supports USB 2.0 full-speed device operation in XTAL-less low-speed mode, eliminating the need for an external 12 MHz crystal. Its integrated USB PHY uses internal timing references calibrated against the 12 MHz IRC oscillator. This feature reduces BOM cost and PCB area-particularly valuable in space-constrained designs like GPS trackers. The LPC11U67JBD100E retains full USB device enumeration and data transfer capability in this mode.

How many ADC input channels does the LPC11U67JBD100E support, and what is its sampling rate?

The LPC11U67JBD100E integrates a single 12-bit successive approximation register (SAR) ADC with up to 12 configurable input channels. It achieves a maximum sample rate of 2 Msamples/s with support for two independent conversion sequences triggered by software, timer, or peripheral events. Channel selection, resolution, and sampling timing are fully programmable via the ADC control registers. This ADC capability is directly applicable in medical monitor designs requiring multi-sensor acquisition.

What low-power modes are available on the LPC11U67JBD100E, and how is wake-up implemented?

The LPC11U67JBD100E provides four low-power modes: Sleep, Deep-sleep, Power-down, and Deep power-down. Wake-up from Deep-sleep and Power-down is supported via external GPIO pins (including dedicated PIO0_16/WAKEUP with 20 ns glitch filter), USART activity (RX edge or break detection), and RTC alarm. In Deep power-down mode, only the RTC and backup registers remain active-requiring VBAT connection for persistent timekeeping. The LPC11U67JBD100E's PMU enables rapid transition between modes with sub-microsecond latency.

Is the LPC11U67JBD100E pin-compatible with other members of the LPC11U6x family?

Yes, the LPC11U67JBD100E shares identical pinout and footprint with other LQFP100 variants in the LPC11U6x family-including LPC11U68JBD100 and LPC11U67JBD100 (non-E suffix). All LQFP100 devices use the SOT407-1 package and maintain consistent signal mapping across GPIO, USB, USART, I²C, SSP, ADC, and power pins. This allows direct substitution within the same package variant for memory or feature scaling, provided firmware accommodates differences in flash/SRAM size and peripheral enablement.