NXP Semiconductors LPC11U67JBD64E
- Part No.:
- LPC11U67JBD64E
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 64-LQFP
- Datasheet:
-
LPC11U67JBD64E.pdf
- Description:
- IC MCU 32BIT 128KB FLASH 64LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:2,958
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC11U67JBD64E from NXP Semiconductors is a 32-bit ARM Cortex-M0+ microcontroller operating at up to 50 MHz, featuring 128 KB flash, 4 KB EEPROM, 20 KB SRAM, one 12-bit ADC with 10 input channels, and full-speed USB 2.0 device controller with on-chip PHY - deployed in GPS trackers and medical monitors requiring low-power, mixed-signal control.
For engineers reviewing the LPC11U67JBD64E datasheet, LPC11U67JBD64E pinout, LPC11U67JBD64E application, or LPC11U67JBD64E equivalent, key selection considerations include its LQFP64 package with 48 GPIOs, dual I²C (one Fast-mode Plus), five USARTs (four with shared fractional baud generator), and dedicated USB PLL enabling crystal-less low-speed USB operation.
Technical Context
The LPC11U67JBD64E implements an ARM Cortex-M0+ core (r0p1) with two-stage pipeline, single-cycle I/O, and integrated NVIC for deterministic interrupt handling. Its AHB multilayer matrix enables concurrent peripheral access without bus contention.
Peripheral architecture includes a configurable PWM/timer subsystem (SCTimer/PWM + four standard timers), CRC engine, DMA with 16 channels, and ROM-based drivers for USB, USART, I²C, and ISP - all supported by a unified power management unit enabling Sleep, Deep-sleep, Power-down, and Deep power-down modes with wake-up via GPIO or USART activity.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M0+ (r0p1), 50 MHz max - delivers energy-efficient execution with single-cycle I/O and fast interrupt response. |
| Memory | 128 KB flash / 4 KB EEPROM / 20 KB SRAM - supports in-application programming (IAP) and robust data retention across power cycles. |
| Analog | 12-bit ADC, 10-channel, 2 Msamples/s - enables high-resolution sensor acquisition with dual conversion sequences and internal/external triggers. |
| USB Interface | Full-speed USB 2.0 device controller with on-chip PHY and XTAL-less low-speed mode - eliminates external crystal for cost-sensitive USB peripherals. |
| Serial Peripherals | 2× I²C (one Fast-mode Plus), 5× USART (4 with shared fractional baud generator), 2× SSP - provides flexible multi-protocol connectivity with DMA support. |
| GPIO & Timers | 48 general-purpose I/O pins with programmable pull-up/down, glitch filter, and open-drain; 6 configurable timers including SCTimer/PWM - supports complex timing, motor control, and signal generation. |
| Power Range | 2.4 V to 3.6 V supply, −40 °C to +105 °C operating temperature - suitable for industrial and automotive-adjacent environments. |
Pinout & Package
LQFP64 package (10 × 10 × 1.4 mm, SOT314-2), 64-pin quad flat lead frame with exposed pad; compatible with standard reflow profiles and automated optical inspection.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (RTCXIN) | RTC oscillator input | Accepts 32.768 kHz crystal for battery-backed real-time clock operation independent of main power domain. |
| 4 (RESET/PIO0_0) | Reset input / GPIO | Active-low reset with 20 ns glitch filter; doubles as debug select (LOW = JTAG, HIGH = SWD) and ISP/USB boot trigger. |
| 28 (SWCLK/PIO0_10) | SWD clock / GPIO | Default Serial Wire Debug clock; configurable as GPIO or SSP0_SCK - enables compact debug interface without JTAG pins. |
| 49–50 (PIO1_13 / SWDIO/PIO0_15) | SWD I/O / GPIO | Dual-function pins for SWD debug communication; also serve as general-purpose I/O or ADC inputs (ADC_3/6). |
| 55 (PIO1_9) | GPIO / ADC_0 | Configurable digital I/O with analog input capability for channel 0 of 12-bit ADC - supports direct sensor interfacing. |
| 25–26 (USB_DM / USB_DP) | USB differential pair | Full-speed USB 2.0 physical layer signals routed internally to on-chip PHY - no external transceiver required. |
| 63 (VBAT) | Battery backup supply | Provides isolated power to RTC domain during main supply loss - maintains timekeeping and alarm functionality. |
Key Features
| Feature | Design Value |
|---|---|
| Crystal-less USB operation | Enables full-speed USB device functionality without external 12 MHz crystal - reduces BOM count and PCB area in portable devices. |
| Dedicated USB PLL | Separate PLL isolates USB clock domain from system clock - ensures jitter-free USB signaling while allowing independent CPU frequency scaling. |
| SCTimer/PWM subsystem | State-configurable timer with 19 PWM outputs and 6 independent time bases - supports advanced motor control, LED dimming, and protocol emulation (e.g., IR, DMX). |
| ROM-based peripheral drivers | Pre-validated USB, USART, I²C, and DMA drivers in on-chip ROM - accelerates firmware development and improves code density and reliability. |
| Deep power-down wake-up | Wakes from <1 µA deep power-down state via PIO0_16/WAKEUP pin with 50 ns pulse detection - ideal for battery-powered remote sensors. |
Applications
| GPS Tracker | Medical Monitor |
|---|---|
Use Scenario: Compact, battery-operated asset tracker acquiring GNSS position, transmitting via cellular modem, and logging motion data. IC Role / Device Role / Timing Role: Central controller managing GPS UART interface, ADC-based battery voltage/temperature sensing, USB configuration port, and low-power sleep/wake scheduling. Use Value: 128 KB flash stores firmware + location history; crystal-less USB simplifies diagnostics; 10-channel ADC monitors multiple health-related analog signals. | Use Scenario: Portable patient vital sign monitor measuring ECG, SpO₂, and temperature with local display and Bluetooth upload. IC Role / Device Role / Timing Role: Mixed-signal hub synchronizing analog front-end sampling, driving OLED display via SPI, and handling USB CDC for PC configuration and firmware updates. Use Value: 12-bit ADC supports clinical-grade signal resolution; 48 GPIOs route multiple sensor interfaces; USB device mode enables plug-and-play host interaction. |
| Car Radio UI Controller | Three-Phase E-Meter |
Use Scenario: Infotainment sub-module controlling touch panel, rotary encoder, audio codec, and CAN bus gateway functions. IC Role / Device Role / Timing Role: Real-time UI processor handling button debouncing, display refresh, audio volume control via PWM, and serial communication with main head unit. Use Value: SCTimer/PWM generates precise audio carrier signals; five USARTs support simultaneous codec, CAN transceiver, and diagnostic interfaces. | Use Scenario: DIN-rail mounted electricity meter measuring voltage, current, and power quality across three phases with tamper detection and data logging. IC Role / Device Role / Timing Role: Metering co-processor performing RMS calculations, harmonic analysis, and secure firmware updates via isolated RS-485 or USB. Use Value: 2 Msamples/s ADC captures high-frequency waveform distortion; EEPROM retains calibration constants and tariff tables across power failures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC11U68JBD64 | 256 KB flash, 36 KB SRAM, same peripherals and package - higher memory capacity with identical pinout and footprint. | Preferred where firmware complexity or data logging depth exceeds 128 KB flash limit. | Select when future firmware expansion or over-the-air update storage is required; no hardware change needed. |
| LPC1343FBD48 | ARM Cortex-M3 core, 72 MHz, 32 KB flash, 8 KB SRAM, LQFP48 - different architecture, lower memory, smaller package, no USB device controller. | Suitable for cost-constrained, non-USB applications needing higher CPU performance but less peripheral integration. | Choose only if USB and EEPROM are unnecessary and M3 instruction set benefits outweigh reduced integration. |
Compared with LPC11U67JBD64E, LPC11U68JBD64 offers scalable memory without layout changes, while LPC1343FBD48 trades USB and EEPROM for raw M3 performance in space-constrained designs - making LPC11U67JBD64E optimal for balanced USB-enabled embedded control.
Availability
LPC11U67JBD64E is available at Aetrix Electronics and suitable for GPS trackers, medical monitors, car radio UI controllers, and three-phase e-meters requiring stable component supply, long-term lifecycle assurance, and industrial temperature grade support.
Supply support for LPC11U67JBD64E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications.
The LPC11U6x product line targets cost-sensitive, low-power embedded systems requiring USB device capability, rich analog integration, and robust firmware update mechanisms - optimized for smart sensors, portable medical devices, and industrial HMI.
FAQ
What is the maximum operating frequency of the LPC11U67JBD64E?
The LPC11U67JBD64E operates at a maximum CPU frequency of 50 MHz using its ARM Cortex-M0+ core. This speed is achieved via the system PLL, which can be driven by the internal 12 MHz IRC oscillator (trimmed to ±1 % accuracy) or an external crystal between 1 MHz and 25 MHz. The LPC11U67JBD64E maintains full peripheral functionality at this rate, including USB full-speed operation enabled by its dedicated USB PLL.
Does the LPC11U67JBD64E support crystal-less USB operation?
Yes, the LPC11U67JBD64E supports XTAL-less low-speed USB mode using its internal oscillator, eliminating the need for an external 12 MHz crystal in basic USB device configurations. However, full-speed USB 2.0 operation requires either the external crystal or the internal IRC oscillator - the dedicated USB PLL ensures stable timing regardless of source. This capability is confirmed in the official NXP LPC11U6x datasheet Rev. 1.5.
How many ADC input channels does the LPC11U67JBD64E provide?
The LPC11U67JBD64E integrates a single 12-bit successive-approximation ADC with up to 10 configurable input channels (ADC_0 through ADC_11, excluding reserved channels). These channels support multiple trigger sources including timers and software, and enable two independent conversion sequences. The ADC achieves sample rates up to 2 Msamples/s - a specification explicitly documented for the LPC11U67JBD64 variant in Table 2 of the NXP datasheet.
What debug interfaces are supported by the LPC11U67JBD64E?
The LPC11U67JBD64E supports Serial Wire Debug (SWD) as the primary debug interface, accessible via pins SWDIO (PIO0_15) and SWCLK (PIO0_10), with optional JTAG boundary scan mode using TRST, TDI, TMS, and TDO pins. SWD is enabled by default and requires only two pins, reducing debug footprint. The part also includes a Micro Trace Buffer (MTB) for instruction trace - all features verified in Section 2 "Features and benefits" of the NXP LPC11U6x datasheet.
Is the LPC11U67JBD64E pin-compatible with other members of the LPC11U6x family?
Yes, the LPC11U67JBD64E is pin-compatible with other LQFP64 variants in the LPC11U6x family, including LPC11U67JBD64 (no suffix) and LPC11U68JBD64. All share identical pin numbering, electrical characteristics, and function mapping per the LQFP64 pinning diagram (Figure 5) and Table 3 "Pin description" in the NXP datasheet. The 'E' suffix denotes enhanced qualification - no functional or mechanical differences affect compatibility.
LPC11U67JBD64E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 64-LQFP
- Series:
- LPC11Uxx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+
- Core Size:
- 32-Bit Single-Core
- Speed:
- 50MHz
- Connectivity:
- I2C, Microwire, SPI, SSI, SSP, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, POR, PWM, WDT
- Number of I/O:
- 48
- Program Memory Size:
- 128KB (128K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 4K x 8
- RAM Size:
- 20K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.4V ~ 3.6V
- Data Converters:
- A/D 10x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC11U67JBD64E FAQ
1.How can I place an order for LPC11U67JBD64E through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC11U67JBD64E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC11U67JBD64E reliable?
The price and inventory of LPC11U67JBD64E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC11U67JBD64E is usually 5 days.
3.What payment methods are accepted for LPC11U67JBD64E?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC11U67JBD64E transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC11U67JBD64E?
LPC11U67JBD64E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC11U67JBD64E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC11U67JBD64E?
For technical support, including LPC11U67JBD64E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC11U67JBD64E requirements.
6.How does Aetrix verify that LPC11U67JBD64E is sourced from the original manufacturer or authorized distributors?
All LPC11U67JBD64E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC11U67JBD64E meets industry standards.
7.What is the process for return or replacement of LPC11U67JBD64E?
All LPC11U67JBD64E units undergo pre-shipment inspection (PSI). If there is an issue with LPC11U67JBD64E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC11U67JBD64E part is unused and in its original packaging.
Return procedure for LPC11U67JBD64E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC11U67JBD64E Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

