NXP Semiconductors LPC1317FBD48,551
- Part No.:
- LPC1317FBD48,551
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 48-LQFP
- Datasheet:
-
LPC1317FBD48,551.pdf
- Description:
- IC MCU 32BIT 64KB FLASH 48LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:188
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC1317FBD48,551 from NXP Semiconductors is a 32-bit ARM Cortex-M3 microcontroller designed for low-power embedded control with USB device capability, 64 kB flash, 8 kB SRAM, and 40 GPIO pins in LQFP48 package. It operates up to 72 MHz, integrates a 12-bit ADC (8 channels, 500 kSamples/s), two SSP interfaces, I²C-bus (Fast-mode Plus, 1 Mbit/s), and a USART supporting RS-485, smart card (ISO 7816-3), and synchronous modes - used in industrial USB peripherals and handheld medical scanners.
For engineers reviewing the LPC1317FBD48,551 datasheet, LPC1317FBD48,551 pinout, LPC1317FBD48,551 application, or LPC1317FBD48,551 equivalent, key selection criteria include its USB 2.0 Full-Speed device controller (no dedicated USB PLL), absence of on-chip EEPROM, 40 GPIO count in LQFP48, and support for Deep power-down wake-up via PIO0_16 - critical for battery-powered portable instrumentation and RS-485 node controllers.
Technical Context
The LPC1317FBD48,551 implements the ARM Cortex-M3 r2p1 core with Harvard architecture, 3-stage pipeline, and integrated NVIC for deterministic interrupt handling. Its clock system combines a 1–25 MHz crystal oscillator, 12 MHz ±1% IRC, and dual PLLs - one for CPU (PLL0) and one dedicated to USB (USB PLL), though the LPC1317 variant excludes the USB PLL per datasheet Table 2.
Peripheral integration includes four general-purpose timers (two 32-bit, two 16-bit), a Windowed WatchDog Timer with internal low-power WDO, and analog subsystem comprising an 8-channel 12-bit ADC with 500 kSamples/s sampling rate. The device supports multiple low-power modes (Sleep, Deep-sleep, Power-down, Deep power-down) managed by an integrated PMU and wake-up via GPIO, watchdog, or USB activity - but USB wake-up is disabled in LPC1317 due to lack of USB PLL and USB transceiver hardware.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M3 r2p1, 3-stage pipeline, Harvard architecture - enables deterministic real-time execution with low interrupt latency. |
| Max Clock Frequency | 72 MHz - achieved via PLL0 using crystal or IRC input; no USB PLL present in LPC1317, limiting USB functionality to device-only mode without dedicated clock synthesis. |
| Memory | 64 kB flash (256-byte page erase), 8 kB SRAM, no EEPROM - supports ISP/IAP via UART/USB bootloader but lacks persistent nonvolatile data storage. |
| Analog Interface | 12-bit ADC, 8 input channels, 500 kSamples/s - sufficient for sensor acquisition in portable medical devices and industrial monitoring nodes. |
| Serial Interfaces | 1× USART (RS-485/9-bit/smart card), 2× SSP (SPI-compatible), 1× I²C-bus (Fast-mode Plus, 1 Mbit/s) - enables multi-protocol fieldbus connectivity without external level shifters. |
| GPIO & Interrupts | 40 programmable GPIO pins (LQFP48), 8 configurable as edge/level-sensitive interrupts, 2 grouped GPIO interrupt modules - supports complex peripheral event handling in compact designs. |
| Power Management | Four reduced-power modes; Deep power-down wake-up via PIO0_16 only - enables ultra-low standby current (<1 µA) in battery-operated handheld scanners. |
Pinout & Package
Package: LQFP48 (SOT313-2), plastic low profile quad flat package, 48 leads, body 7 × 7 × 1.4 mm, operating temperature −40 °C to +85 °C, single 3.3 V supply (2.0 V to 3.6 V).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RESET/PIO0_0 | Reset input / General-purpose I/O | Active-Low reset with 20 ns glitch filter; also debug select (LOW = JTAG, HIGH = SWD); default state is input with pull-up. |
| SWDIO/PIO0_15/AD4/CT32B1_MAT2 | Debug I/O / ADC input / Timer match output | Primary debug interface pin (Serial Wire Debug); shares function with ADC channel 4 and 32-bit timer 1 match output 2 - requires careful signal routing in debug-enabled production firmware. |
| PIO0_16/AD5/CT32B1_MAT3/WAKEUP | ADC input / Timer match output / Wake-up trigger | Dedicated Deep power-down wake-up pin with 20 ns glitch filter; must be pulled HIGH to enter and LOW to exit DPD mode - critical for battery life optimization in portable instruments. |
| PIO0_4/SCL & PIO0_5/SDA | I²C-bus clock/data | Open-drain I²C pins supporting Fast-mode Plus (1 Mbit/s); high-current sink enabled only when Fast-mode Plus is configured in IOCON - ensures robust bus driving without external pull-ups in noisy environments. |
| PIO0_18/RXD & PIO0_19/TXD | USART receive/transmit | Full-duplex UART interface supporting RS-485 half-duplex mode and asynchronous smart card (ISO 7816-3); RXD doubles as UART ISP entry pin - enables field firmware updates without debugger. |
Key Features
| Feature | Design Value |
|---|---|
| ARM Cortex-M3 NVIC | Hardware-accelerated nested interrupt handling with configurable priority - reduces ISR latency to <12 cycles for time-critical motor control loops. |
| Programmable Glitch Filter | Eight GPIO pins support software-configurable digital noise suppression - eliminates false triggers from EMI in industrial RS-485 gateways. |
| High-Current GPIO Drivers | P0_7 provides 20 mA source; P0_4/P0_5 provide 20 mA sink in Fast-mode Plus mode - directly drives LEDs or I²C bus capacitance without external buffers. |
| Repetitive Interrupt Timer (RI Timer) | Dedicated low-overhead timer for periodic OS tick or sensor polling - frees main CPU timers for application-specific timing tasks. |
| Boot ROM API Support | 16 kB ROM includes USB API, power control, flash IAP/ISP, and EEPROM emulation functions - accelerates development of secure firmware update mechanisms. |
Applications
| Industrial RS-485 Node Controller | Portable Medical Sensor Hub |
|---|---|
Use Scenario: Compact DIN-rail mounted node aggregating temperature, pressure, and flow sensors across factory floor via RS-485 daisy chain. IC Role / Device Role / Timing Role: Central MCU executing Modbus RTU protocol, managing ADC sampling, and controlling isolated RS-485 transceiver enable timing. Use Value: 40 GPIO allow direct connection to 8-channel ADC and dual SSP buses for SPI-based sensor expansion; USART RS-485 mode with automatic direction control simplifies hardware design. |
Use Scenario: Handheld blood glucose or pulse oximeter with LCD display, button interface, and USB data export to PC. IC Role / Device Role / Timing Role: System controller handling analog sensor signal conditioning, user interface management, and USB Full-Speed device enumeration. Use Value: Integrated USB 2.0 device controller enables plug-and-play data logging without external PHY; Deep power-down mode extends battery life beyond 100 hours on coin cell. |
| USB Audio Peripheral | Consumer Handheld Scanner |
Use Scenario: Low-cost USB microphone or speaker dock requiring audio streaming without external codec. IC Role / Device Role / Timing Role: USB device endpoint manager interfacing with external I²S audio codec and handling USB audio class descriptors. Use Value: USB Full-Speed device controller with ROM-based driver library reduces firmware size; I²C Fast-mode Plus supports fast configuration of audio codec registers. |
Use Scenario: Barcode scanner with laser diode driver, photodiode amplifier, and USB HID keyboard emulation. IC Role / Device Role / Timing Role: Real-time decoder engine processing scanned waveform, generating HID reports, and managing low-latency USB interrupt transfers. Use Value: 72 MHz Cortex-M3 delivers >200 kbps decode throughput; 12-bit ADC samples photodiode signals at 500 kSamples/s for high-resolution bar pattern capture. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC1347FBD48 | Includes USB PLL and full USB 2.0 transceiver; adds 2 kB EEPROM; same 64 kB flash/8 kB SRAM/40 GPIO. | Supports USB host/device dual-role and precise USB clock synchronization; required for USB audio class compliance. | Select LPC1347FBD48 when USB device timing accuracy or EEPROM-based parameter storage is mandatory. |
| LPC1316FBD48 | 48 kB flash, no USB controller, identical package and peripheral set otherwise. | Suitable for cost-sensitive RS-485 or I²C-only nodes where USB is unnecessary. | Choose LPC1316FBD48 to reduce BOM cost while retaining ADC, timers, and low-power features for non-USB industrial sensing. |
Compared with LPC1317FBD48,551, the LPC1347FBD48 adds USB clock precision and nonvolatile storage at higher unit cost, while the LPC1316FBD48 removes USB entirely to lower price - making LPC1317FBD48,551 the optimal balance for USB-capable portable instrumentation needing no EEPROM.
Availability
LPC1317FBD48,551 is available at Aetrix Electronics and suitable for industrial RS-485 node controllers, portable medical sensor hubs, and consumer handheld scanners requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for LPC1317FBD48,551 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The LPC1300 series targets cost-effective, low-power embedded control applications requiring USB device connectivity, rich analog integration, and robust real-time performance - exemplified by the LPC1317FBD48,551's focus on portable instrumentation and industrial field devices.
FAQ
Does LPC1317FBD48,551 support USB host functionality?
No. The LPC1317FBD48,551 implements only a USB 2.0 Full-Speed device controller with no USB OTG or host capability. It lacks the USB PLL and transceiver hardware required for host operation. Applications requiring USB host must use LPC17xx or LPC18xx families. The LPC1317FBD48,551 is strictly a USB device endpoint.
What is the maximum ADC sampling rate achievable on LPC1317FBD48,551?
The LPC1317FBD48,551 supports a maximum ADC sampling rate of 500 kSamples/s across its 8 input channels. This rate is achievable in burst mode with optimized clock configuration and minimal conversion overhead. The actual sustained throughput depends on software handling of conversion complete interrupts and data buffering - the LPC1317FBD48,551's 8 kB SRAM provides adequate space for real-time acquisition buffers.
Can LPC1317FBD48,551 enter Deep power-down mode and wake up via USB activity?
No. Unlike LPC134x variants, the LPC1317FBD48,551 does not include the USB PLL or full USB transceiver, so USB activity cannot trigger wake-up from Deep power-down mode. Valid wake-up sources are PIO0_16 (WAKEUP pin), reset, watchdog interrupt, or selected GPIO pins - as confirmed in Section 2.7 "Power control" of the datasheet. USB-related wake-up is unavailable on LPC1317FBD48,551.
Is there on-chip EEPROM in LPC1317FBD48,551?
No. The LPC1317FBD48,551 has no on-chip EEPROM memory. Table 2 in the datasheet explicitly lists EEPROM as "-" for all LPC131x variants. Persistent data storage must be implemented externally or emulated in flash using NXP's IAP routines - a design constraint clearly distinguishing LPC1317FBD48,551 from LPC134x parts which include 2 kB EEPROM.
What debug interfaces are supported by LPC1317FBD48,551?
The LPC1317FBD48,551 supports Serial Wire Debug (SWD) and standard JTAG interfaces. SWD uses SWCLK (PIO0_10) and SWDIO (PIO0_15) pins; JTAG uses TDI, TDO, TMS, TRST, and TCK (mapped to PIO0_11, PIO0_13, PIO0_12, PIO0_14, and PIO0_10 respectively). Both are fully functional for programming and real-time debugging - the LPC1317FBD48,551 does not require external debug probes beyond standard ARM-compliant adapters.
LPC1317FBD48,551 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 48-LQFP
- Series:
- LPC13xx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 72MHz
- Connectivity:
- I2C, Microwire, SPI, SSI, SSP, UART/USART
- Peripherals:
- Brown-out Detect/Reset, POR, WDT
- Number of I/O:
- 40
- Program Memory Size:
- 64KB (64K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 4K x 8
- RAM Size:
- 10K x 8
- Voltage - Supply (Vcc/Vdd):
- 2V ~ 3.6V
- Data Converters:
- A/D 8x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC1317FBD48,551 FAQ
1.How can I place an order for LPC1317FBD48,551 through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC1317FBD48,551 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC1317FBD48,551 reliable?
The price and inventory of LPC1317FBD48,551 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC1317FBD48,551 is usually 5 days.
3.What payment methods are accepted for LPC1317FBD48,551?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC1317FBD48,551 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC1317FBD48,551?
LPC1317FBD48,551 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC1317FBD48,551 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC1317FBD48,551?
For technical support, including LPC1317FBD48,551 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC1317FBD48,551 requirements.
6.How does Aetrix verify that LPC1317FBD48,551 is sourced from the original manufacturer or authorized distributors?
All LPC1317FBD48,551 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC1317FBD48,551 meets industry standards.
7.What is the process for return or replacement of LPC1317FBD48,551?
All LPC1317FBD48,551 units undergo pre-shipment inspection (PSI). If there is an issue with LPC1317FBD48,551, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC1317FBD48,551 part is unused and in its original packaging.
Return procedure for LPC1317FBD48,551:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC1317FBD48,551 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

