NXP Semiconductors LPC1343FBD48,151

Overview

LPC1343FBD48,151 from NXP Semiconductors is a 32-bit ARM Cortex-M3 microcontroller in LQFP48 package, operating at up to 72 MHz with 32 kB flash, 8 kB SRAM, USB 2.0 full-speed device controller (on-chip PHY), one UART with RS-485 support, one Fast-mode Plus I²C-bus interface (1 Mbit/s), and 42 GPIO pins. It targets embedded control applications requiring integrated USB connectivity and low-power operation.

For engineers reviewing the LPC1343FBD48,151 datasheet, LPC1343FBD48,151 pinout, LPC1343FBD48,151 application, or LPC1343FBD48,151 equivalent, key selection considerations include USB device capability, 10-bit ADC with 8-channel multiplexing, dual SSP controllers (SSP0 + SSP1 on LPC1313FBD48/01 only - not applicable here), and Deep power-down wake-up via dedicated GPIO pins.

Technical Context

The LPC1343FBD48,151 implements the ARM Cortex-M3 core with Harvard architecture, 3-stage pipeline, and internal prefetch unit supporting speculative branching. Its peripheral set includes a USB 2.0 full-speed device controller with integrated PHY, UART with fractional baud rate generation and RS-485/EIA-485 support, and Fast-mode Plus I²C-bus interface compliant with I²C specification at 1 Mbit/s data rate.

Power management features include three reduced-power modes (Sleep, Deep-sleep, Deep power-down), programmable Brownout Detect with four interrupt thresholds, and an integrated Power Management Unit (PMU). The device supports In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader, with boot selection between UART and USB interfaces.

Key Specifications

Pinout & Package

LPC1343FBD48,151 is housed in a 48-pin LQFP package (SOT313-2), body size 7 × 7 × 1.4 mm, with exposed pad for thermal dissipation. Pin functions are defined per NXP's official LPC1311_13_42_43 datasheet Rev. 5 (June 2012).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microcontroller applications.

Compared with LPC1342FBD48 and LPC1313FBD48/01, the LPC1343FBD48,151 uniquely delivers USB device functionality alongside full 32 kB flash and 8 kB SRAM - making it the only option in the LPC13xx LQFP48 family that combines USB 2.0 full-speed capability with maximum on-chip memory for feature-rich embedded applications.

Availability

LPC1343FBD48,151 is available at Aetrix Electronics and suitable for eMetering, lighting control, alarm systems, and white goods requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.

Supply support for LPC1343FBD48,151 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.

The LPC1300 series, including LPC1343FBD48,151, was designed for cost-sensitive, low-power embedded applications demanding ARM Cortex-M3 performance, USB device integration, and robust peripheral sets - particularly targeting smart meters, home appliances, and industrial HMI systems.

FAQ

Does LPC1343FBD48,151 support USB host functionality?

No. The LPC1343FBD48,151 integrates only a USB 2.0 full-speed device controller with on-chip PHY. It does not support USB host or OTG modes. Applications requiring host capability must use other NXP families such as LPC17xx or LPC18xx. The LPC1343FBD48,151 is strictly configured for peripheral-side USB communication.

What is the maximum operating voltage range for LPC1343FBD48,151?

The LPC1343FBD48,151 operates from a single 2.0 V to 3.6 V supply. VDD must be within this range; exceeding 3.6 V risks permanent damage. The ADC reference is tied to VDD, so analog accuracy scales with supply stability. The LPC1343FBD48,151 does not support 5 V I/O - all GPIOs are 5 V tolerant only in digital input mode, not as outputs.

Can LPC1343FBD48,151 enter Deep power-down mode and wake up via USB activity?

No. USB activity cannot wake the LPC1343FBD48,151 from Deep power-down mode. Wake-up is supported only via dedicated GPIO pins (up to 40 functional pins), RTC alarm, or WAKEUP pin (PIO1_4). USB functionality is disabled in Deep power-down. To maintain USB responsiveness, use Deep-sleep mode instead - where USB PHY remains powered and can generate interrupts.

Is there a hardware bootloader for LPC1343FBD48,151, and how is it triggered?

Yes. The LPC1343FBD48,151 includes an on-chip ISP bootloader activated by asserting specific pin states at reset: a LOW on PIO0_3/USB_VBUS selects USB enumeration mode; a LOW on PIO0_1/CLKOUT enters UART ISP mode. No external programmer is needed for initial firmware loading. The LPC1343FBD48,151 supports both UART- and USB-based firmware updates in the field.

Does LPC1343FBD48,151 include a hardware floating-point unit (FPU)?

No. The LPC1343FBD48,151 uses the base ARM Cortex-M3 core without an integrated FPU. All floating-point operations are handled in software using CMSIS-DSP libraries or compiler-generated routines. For applications requiring hardware-accelerated math, consider Cortex-M4-based alternatives like LPC43xx or LPC54xxx series.