NXP Semiconductors LPC1346FHN33,551
- Part No.:
- LPC1346FHN33,551
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 32-VQFN Exposed Pad
- Datasheet:
-
LPC1346FHN33,551.pdf
- Description:
- IC MCU 32BIT 48KB FLASH 32HVQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LPC1346FHN33,551 from NXP Semiconductors is a 32-bit ARM Cortex-M3 microcontroller designed for USB-enabled embedded control applications. It operates at up to 72 MHz, integrates 48 kB flash, 8 kB SRAM, 2 kB EEPROM, a full-speed USB 2.0 device controller with ROM-based driver library, and an 8-channel 12-bit ADC sampling at 500 kSamples/s. It targets compact, low-power USB peripheral designs such as handheld scanners and medical sensors.
For engineers reviewing the LPC1346FHN33,551 datasheet, LPC1346FHN33,551 pinout, LPC1346FHN33,551 application, or LPC1346FHN33,551 equivalent, key selection criteria include its HVQFN33 package footprint, USB device capability without external PHY, 26 GPIO pins in this variant, and support for ISP/IAP via USB - critical for field-upgradable consumer and industrial edge devices.
Technical Context
The LPC1346FHN33,551 implements the ARM Cortex-M3 r2p1 core with Harvard architecture, 3-stage pipeline, and integrated NVIC for deterministic interrupt handling. Its clock system includes dual PLLs - one for CPU (up to 72 MHz) and a dedicated USB PLL - enabling simultaneous high-speed processing and robust USB 2.0 full-speed operation at 48 MHz.
Digital peripherals include two SSP controllers with FIFOs, a Fast-mode Plus I²C-bus interface (1 Mbit/s), and four general-purpose timers (two 16-bit, two 32-bit) with match/capture functionality. Analog integration centers on a single 12-bit ADC with eight inputs and programmable sampling rates, while power management supports Sleep, Deep-sleep, Power-down, and Deep power-down modes with wake-up via GPIO, watchdog, or USB activity.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M3 r2p1, 72 MHz max - enables real-time deterministic control with low-latency interrupt response. |
| Memory | 48 kB flash / 8 kB SRAM / 2 kB EEPROM - sufficient for USB stack + application firmware with non-volatile parameter storage. |
| USB Interface | Full-speed USB 2.0 device controller with ROM-based API - eliminates need for external transceiver or USB firmware stack development. |
| ADC | 12-bit, 8-channel, 500 kSamples/s - supports high-resolution sensor acquisition in portable medical or industrial monitoring. |
| Timers | Four general-purpose timers (2×16-bit, 2×32-bit) with up to 13 match outputs and 8 capture inputs - enables precise PWM generation and input signal timing analysis. |
| I/O & Packaging | 26 GPIO pins in HVQFN33 (7 × 7 × 0.85 mm) - provides compact board area with thermal enhancement for space-constrained USB peripherals. |
| Power Supply | Single 3.3 V supply (2.0–3.6 V), −40 °C to +85 °C - suitable for battery-powered and industrial ambient environments. |
Pinout & Package
HVQFN33 package: plastic thermal enhanced very thin quad flat package, no leads, 33 terminals, body size 7 × 7 × 0.85 mm. Pin 1 index area marked; exposed thermal pad recommended for PCB thermal relief.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RESET/PIO0_0 | Reset input / GPIO | Active-low reset with 20 ns glitch filter; also selects JTAG vs SWD debug mode during boot. |
| SWDIO/PIO0_15/AD4/CT32B1_MAT2 | Debug I/O / ADC / Timer | Serial Wire Debug bidirectional pin; also serves as ADC input 4 and 32-bit timer 1 match output 2. |
| USB_DP / USB_DM | USB differential pair | Full-speed USB 2.0 data lines - require 27 Ω series resistors and proper 90 Ω differential impedance routing. |
| USB_VBUS / USB_CONNECT | VBUS sense / Connect control | PIO0_3 senses VBUS presence; PIO0_6 controls internal pull-up on D+ to signal USB connect to host. |
| XTALIN / XTALOUT | Clock oscillator interface | Supports 1–25 MHz crystal; internal oscillator failure detector ensures system clock reliability. |
| VDD / VSS | Power / Ground | Three VDD pins (pins 8, 17, 32) and one VSS (pin 33) - decoupling required per pin with 100 nF ceramic capacitors. |
Key Features
| Feature | Design Value |
|---|---|
| Dual PLL architecture | Dedicated USB PLL isolates USB timing from CPU clock domain, ensuring stable 48 MHz USB operation independent of CPU frequency scaling. |
| In-Application Programming (IAP) | On-chip bootloader enables firmware updates over USB without external programmer - essential for remote maintenance of deployed devices. |
| Fast-mode Plus I²C | 1 Mbit/s bus speed with multi-address recognition and monitor mode - supports high-bandwidth sensor networks and legacy I²C peripheral compatibility. |
| Programmable Windowed Watchdog | Configurable timeout window prevents accidental resets while detecting software hangs - improves reliability in unattended medical or industrial systems. |
| Deep power-down wake-up | Single-pin (PIO0_16/WAKEUP) wake-up from Deep power-down mode with 50 ns pulse - enables ultra-low-power sensor nodes with event-triggered activation. |
Applications
| USB Audio Interface | Handheld Medical Scanner |
|---|---|
Use Scenario: Compact USB audio device (e.g., headset adapter or microphone preamp) requiring plug-and-play host recognition without drivers. IC Role / Device Role / Timing Role: USB 2.0 full-speed device controller handles enumeration and audio streaming; Cortex-M3 processes gain control and digital filtering in real time. Use Value: Integrated USB PHY and ROM-based driver reduce BOM cost and eliminate external transceiver, accelerating time-to-market for Class 1 audio accessories. | Use Scenario: Portable infrared or optical scanner used in point-of-care diagnostics with battery operation and Bluetooth/USB data export. IC Role / Device Role / Timing Role: Central controller managing ADC sampling of sensor array, USB mass storage emulation for image transfer, and low-power sleep between scans. Use Value: 2 kB EEPROM stores calibration coefficients; Deep power-down mode extends battery life beyond 100 hours between charges. |
| Industrial RS-485 Gateway | Consumer Peripheral Hub |
Use Scenario: Small-form-factor gateway converting Modbus RTU over RS-485 to USB CDC ACM for PC-based SCADA systems. IC Role / Device Role / Timing Role: USART with RS-485/EIA-485 support and synchronous smart card interface manages half-duplex bus timing; USB handles host communication. Use Value: Single-chip solution replaces discrete UART + USB bridge ICs, reducing layout complexity and EMI susceptibility in noisy factory environments. | Use Scenario: Multi-function USB hub for gaming peripherals (keyboard, mouse, headset) with onboard LED control and firmware-updatable profiles. IC Role / Device Role / Timing Role: MCU executes HID report parsing, RGB LED PWM control via timer match outputs, and USB descriptor handling. Use Value: 26 GPIO pins support direct LED matrix drive and button scanning; 48 kB flash accommodates multiple lighting effects and user profile storage. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC1347FHN33 | 64 kB flash, USB device + host capability, same HVQFN33 package and pinout. | Required when USB host functionality (e.g., USB flash drive reader) or larger firmware image is needed. | Select LPC1347FHN33 if future firmware growth or dual-role USB is anticipated; otherwise LPC1346FHN33,551 offers optimal cost/performance balance. |
| LPC11U37FHN33 | ARM Cortex-M0 core, 64 kB flash, USB device only, same HVQFN33 package but different pin mapping and reduced peripheral set. | Suitable for simpler USB HID applications where lower performance and fewer timers/ADC channels are acceptable. | Choose LPC11U37FHN33 for cost-sensitive, low-complexity USB peripherals; avoid if 72 MHz processing or advanced timer features are required. |
Compared with LPC1347FHN33, the LPC1346FHN33,551 trades 16 kB flash and USB host capability for lower unit cost and identical USB device functionality; versus LPC11U37FHN33, it delivers higher real-time throughput and richer analog/digital peripheral integration at the expense of slightly higher power in active mode.
Availability
LPC1346FHN33,551 is available at Aetrix Electronics and suitable for USB peripheral design, handheld medical instrumentation, and industrial RS-485-to-USB gateway applications requiring stable component supply and long-term manufacturability.
Supply support for LPC1346FHN33,551 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The LPC1300 series was designed specifically for cost-effective, USB-integrated microcontroller applications in consumer electronics and portable industrial equipment - emphasizing minimal external components, low power, and rapid USB deployment.
FAQ
What USB speed and device class does the LPC1346FHN33,551 support?
The LPC1346FHN33,551 supports USB 2.0 full-speed (12 Mbps) as a device only, with built-in hardware controller and ROM-based USB device stack supporting CDC, HID, and MSC classes. It does not support USB host or high-speed modes. The LPC1346FHN33,551 requires no external transceiver and uses internal pull-ups for enumeration.
Does the LPC1346FHN33,551 include an internal EEPROM, and how is it accessed?
Yes, the LPC1346FHN33,551 integrates 2 kB of on-chip EEPROM with dedicated API support in boot ROM. It is accessed via IAP commands through the ISP bootloader or directly from application code using the ROM API functions - enabling reliable non-volatile storage of calibration data or configuration parameters without external memory.
How many GPIO pins are available on the LPC1346FHN33,551 in the HVQFN33 package?
The LPC1346FHN33,551 provides 26 GPIO pins in the HVQFN33 package. These include configurable pull-up/pull-down resistors, repeater mode, input inverters, pseudo open-drain mode, and eight pins with programmable glitch filters. Eight GPIOs can be selected as edge/level-sensitive interrupt sources.
What debug interfaces are supported by the LPC1346FHN33,551?
The LPC1346FHN33,551 supports Serial Wire Debug (SWD) and standard JTAG interfaces, both accessible via dedicated pins (SWDIO/PIO0_15 and SWCLK/PIO0_10). It also supports ETM time stamping for trace analysis. SWD is the recommended interface due to its 2-pin footprint and full debug capability, while JTAG remains available for boundary scan testing.
Can the LPC1346FHN33,551 operate without an external crystal?
Yes, the LPC1346FHN33,551 can operate using its internal 12 MHz IRC oscillator, trimmed to ±1 % accuracy across voltage and temperature. This allows crystal-free operation for non-USB applications. However, USB functionality requires the external crystal (1–25 MHz) to generate the precise 48 MHz clock via the dedicated USB PLL - the IRC alone cannot meet USB timing requirements.
LPC1346FHN33,551 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 32-VQFN Exposed Pad
- Series:
- LPC13xx
- Packaging:
- Bulk
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 72MHz
- Connectivity:
- I2C, Microwire, SPI, SSI, SSP, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, POR, WDT
- Number of I/O:
- 26
- Program Memory Size:
- 48KB (48K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 4K x 8
- RAM Size:
- 10K x 8
- Voltage - Supply (Vcc/Vdd):
- 2V ~ 3.6V
- Data Converters:
- A/D 8x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC1346FHN33,551 FAQ
1.How can I place an order for LPC1346FHN33,551 through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC1346FHN33,551 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC1346FHN33,551 reliable?
The price and inventory of LPC1346FHN33,551 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC1346FHN33,551 is usually 5 days.
3.What payment methods are accepted for LPC1346FHN33,551?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC1346FHN33,551 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC1346FHN33,551?
LPC1346FHN33,551 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC1346FHN33,551 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC1346FHN33,551?
For technical support, including LPC1346FHN33,551 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC1346FHN33,551 requirements.
6.How does Aetrix verify that LPC1346FHN33,551 is sourced from the original manufacturer or authorized distributors?
All LPC1346FHN33,551 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC1346FHN33,551 meets industry standards.
7.What is the process for return or replacement of LPC1346FHN33,551?
All LPC1346FHN33,551 units undergo pre-shipment inspection (PSI). If there is an issue with LPC1346FHN33,551, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC1346FHN33,551 part is unused and in its original packaging.
Return procedure for LPC1346FHN33,551:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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