NXP Semiconductors LPC1347FHN33,551
- Part No.:
- LPC1347FHN33,551
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 32-VQFN Exposed Pad
- Datasheet:
-
LPC1347FHN33,551.pdf
- Description:
- IC MCU 32BIT 64KB FLASH 32HVQFN
- Quantity:
- Payment:

- Shipping:

Inventory:485
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Product details
Overview
LPC1347FHN33 from NXP Semiconductors is a 32-bit ARM Cortex-M3 microcontroller designed for USB-enabled embedded control applications. It operates at up to 72 MHz, integrates 64 kB flash, 8 kB SRAM, 2 kB EEPROM, a full-speed USB 2.0 device controller, and an 8-channel 12-bit ADC with 500 kSamples/s sampling rate - enabling compact, low-power USB audio devices and industrial sensor interfaces.
For engineers reviewing the LPC1347FHN33 datasheet, LPC1347FHN33 pinout, LPC1347FHN33 application, or LPC1347FHN33 equivalent, key selection criteria include its HVQFN33 package with 26 GPIO pins, dual SSP and I²C-FM+ interfaces, USB PLL support, and wake-up capability from Deep power-down via dedicated WAKEUP pin (PIO0_16).
Technical Context
The LPC1347FHN33 implements the ARM Cortex-M3 r2p1 core with Harvard architecture, 3-stage pipeline, and integrated NVIC for deterministic interrupt handling. Its clock system includes a 1–25 MHz crystal oscillator, 12 MHz ±1% IRC, programmable PLLs (one for CPU, one dedicated for USB), and a low-power watchdog oscillator.
Peripheral integration includes two SSP controllers with FIFOs, a Fast-mode Plus I²C-bus interface (1 Mbit/s), a USART supporting RS-485/ISO 7816 smart card mode, four general-purpose timers (two 16-bit, two 32-bit), and a Windowed Watchdog Timer with glitch-filtered wake-up inputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M3 r2p1, 72 MHz max operation - enables real-time deterministic control in resource-constrained systems. |
| Memory | 64 kB flash (256-byte page erase), 8 kB SRAM, 2 kB EEPROM - supports field firmware updates via USB/IAP and non-volatile parameter storage. |
| USB Interface | Full-Speed USB 2.0 device controller with ROM-based driver library - eliminates external PHY and reduces BOM for HID/audio/class-compliant peripherals. |
| Analog | 12-bit ADC, 8 channels, 500 kSamples/s - sufficient resolution and speed for multi-sensor monitoring without external oversampling. |
| Digital I/O | 26 GPIO pins in HVQFN33 package, 8 with programmable glitch filter, 20 mA sink/source on select pins - direct drive of LEDs, relays, or level-shifted signals. |
| Power Modes | Four reduced-power modes (Sleep, Deep-sleep, Power-down, Deep power-down) with wake-up via GPIO, USB activity, or WAKEUP pin - extends battery life in portable USB devices. |
| Package | HVQFN33 (7 × 7 × 0.85 mm, 33 terminals, thermal pad) - compact footprint suitable for space-limited USB dongles and handheld scanners. |
Pinout & Package
HVQFN33 package: 7 mm × 7 mm body, 0.85 mm height, exposed thermal pad, 33 terminals. Pin 1 index area marked; terminal 33 = VSS (ground). Thermal pad must be soldered to PCB ground plane for reliable operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (VSS) | Ground reference | Primary digital ground return; connects to PCB ground plane via thermal pad for thermal and EMI performance. |
| 2 (PIO0_0/RESET) | Reset input / debug select | Active-low reset with 20 ns glitch filter; HIGH selects SWD debug mode, LOW selects JTAG boundary scan. |
| 3 (PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE) | Multi-function output | Configurable as clock output, timer match signal, or USB frame toggle indicator - simplifies USB protocol debugging. |
| 9 (PIO0_3/USB_VBUS) | USB voltage detection | Monitors USB VBUS presence (5 V tolerant); used to auto-enable USB stack and enter device mode upon cable insertion. |
| 15 (PIO0_6/USB_CONNECT/SCK0) | USB connection control | Drives internal pull-up on D+ to signal USB connect event to host; also serves as SSP0 clock in non-USB contexts. |
| 25 (SWDIO/PIO0_15/AD4/CT32B1_MAT2) | Debug/analog/timer I/O | Shared serial wire debug I/O, ADC input channel 4, and 32-bit timer 1 match output - enables in-circuit debug without dedicated debug header. |
| 26 (PIO0_16/AD5/CT32B1_MAT3/WAKEUP) | Wake-up trigger | Dedicated Deep power-down wake-up pin with 20 ns glitch filter; must be pulled HIGH to enter and LOW to exit deep sleep - ensures ultra-low standby current. |
| 32 (USB_DM) | USB differential data- | Low-voltage differential signal line; requires controlled 90 Ω impedance trace and matched length with USB_DP for full-speed compliance. |
| 33 (USB_DP) | USB differential data+ | Low-voltage differential signal line; routed with USB_DM as tightly coupled pair to meet USB 2.0 full-speed eye diagram requirements. |
Key Features
| Feature | Design Value |
|---|---|
| On-chip USB 2.0 Full-Speed Device Controller | Eliminates need for external USB PHY; ROM-based driver library reduces firmware development time for HID, CDC, or custom class devices. |
| Dual SSP Interfaces with FIFO | Enables simultaneous communication with multiple SPI peripherals (e.g., display + sensor) without CPU overhead or FIFO overflow risk. |
| I²C Fast-mode Plus (1 Mbit/s) | Supports high-speed sensor or EEPROM communication while maintaining compatibility with standard I²C slaves and multi-master arbitration. |
| Programmable Windowed Watchdog Timer (WWDT) | Prevents runaway code execution with configurable time window - critical for fail-safe industrial control and medical peripherals. |
| USB PLL + CPU PLL Independence | Allows USB clock (48 MHz) and CPU clock (up to 72 MHz) to operate from separate PLL sources - avoids timing conflicts during dynamic frequency scaling. |
| Boot ROM API Support | Provides standardized functions for USB, EEPROM, flash IAP/ISP, and power control - accelerates secure firmware update implementation. |
Applications
| USB Audio Adapters | Industrial Sensor Gateways |
|---|---|
|
Use Scenario: Compact USB-to-analog audio interface for PC headsets or conference systems. IC Role / Device Role / Timing Role: USB device controller handles enumeration and streaming; 12-bit ADC digitizes analog mic input; USART configures external codec. Use Value: Integrated USB PHY replacement and 500 kSamples/s ADC enable single-chip audio capture without external converters or transceivers. |
Use Scenario: DIN-rail mounted sensor node aggregating temperature, humidity, and vibration data for factory floor monitoring. IC Role / Device Role / Timing Role: MCU reads multi-sensor I²C/FM+ and SPI data; USB provides plug-and-play configuration and bulk data upload; WWDT ensures runtime reliability. Use Value: 26 GPIO, dual SSP, and I²C-FM+ allow direct connection to 8+ sensors; Deep power-down mode extends battery life in wireless variants. |
| Handheld Barcode Scanners | Medical Diagnostic Peripherals |
|
Use Scenario: Battery-powered scanner with laser/CMOS imager, USB HID keyboard emulation, and button-triggered decode. IC Role / Device Role / Timing Role: GPIO manages trigger, LED, and imager enable; USB HID class handles keystroke injection; timers synchronize decode timing. Use Value: High-current GPIO (20 mA) drives visible status LEDs directly; USB_FTOGGLE pin simplifies frame synchronization during HID report transmission. |
Use Scenario: Portable ECG or pulse oximeter module connecting to clinical tablets via USB for waveform visualization and storage. IC Role / Device Role / Timing Role: ADC samples biopotential signals at ≥1 kS/s; USB CDC class streams real-time data; WAKEUP pin enables instant-on from standby when sensor detects patient contact. Use Value: Medical-grade 12-bit ADC with 8 channels supports multi-lead acquisition; -40°C to +85°C rating ensures operation in clinical environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC1343FHN33 | 32 kB flash, no USB controller, same HVQFN33 package and peripheral set except USB/USB PLL. | Suitable for cost-sensitive, non-USB designs requiring identical footprint and GPIO count. | Select when USB connectivity is unnecessary and flash budget is ≤32 kB. |
| LPC1347FBD48 | Same core, memory, and peripherals but in LQFP48 package with 40 GPIO pins and additional CT32B0_CAP1/CT16B1_CAP1 inputs. | Better suited for designs needing more GPIO, capture inputs, or board-level debug access via exposed JTAG pins. | Choose for prototyping or applications requiring expanded I/O or legacy JTAG toolchain support. |
Compared with LPC1347FHN33, the LPC1343FHN33 removes USB functionality to reduce cost and power, while the LPC1347FBD48 trades compactness for higher I/O count and enhanced timer capture capability - both retain identical ARM Cortex-M3 architecture and software compatibility.
Availability
LPC1347FHN33 is available at Aetrix Electronics and suitable for USB audio devices, industrial sensor gateways, and handheld scanners requiring stable component supply, long-term lifecycle assurance, and consistent parametric performance across production batches.
Supply support for LPC1347FHN33 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with headquarters in Eindhoven, Netherlands.
The LPC1300 series was designed specifically for cost-effective, USB-integrated embedded control - balancing ARM Cortex-M3 performance, low-power operation, and minimal external component count for consumer and industrial peripherals.
FAQ
What is the maximum operating frequency of the LPC1347FHN33?
The LPC1347FHN33 operates at a maximum CPU frequency of 72 MHz, achieved using either the internal 12 MHz ±1% IRC oscillator or an external crystal (1–25 MHz) with the integrated PLL. This frequency is sustained across the full industrial temperature range (−40 °C to +85 °C) and 2.0 V to 3.6 V supply voltage.
Does the LPC1347FHN33 support USB device functionality without external components?
Yes, the LPC1347FHN33 integrates a full-speed USB 2.0 device controller with on-chip ROM-based driver library, requiring only passive termination resistors and proper PCB layout for USB_DP/USB_DM. No external PHY or transceiver is needed, reducing BOM and board area for USB HID, CDC, or MSC class devices.
How many analog input channels does the LPC1347FHN33 ADC support?
The LPC1347FHN33 features a single 12-bit successive-approximation ADC with eight input channels (AD0–AD7), capable of sampling at up to 500 kSamples/s. All channels are accessible in the HVQFN33 package, with AD0–AD5 mapped to PIO0_11 through PIO0_16, and AD6–AD7 on PIO0_22 and PIO0_23.
What debug interfaces are supported by the LPC1347FHN33?
The LPC1347FHN33 supports Serial Wire Debug (SWD) as the primary debug interface, with SWDIO and SWCLK available on PIO0_15 and PIO0_10. JTAG is also supported via TDI, TDO, TMS, TRST, and TCK pins, though SWD is recommended for its 2-pin efficiency and full debug capability including flash programming and real-time tracing.
Can the LPC1347FHN33 enter and wake from Deep power-down mode?
Yes, the LPC1347FHN33 supports Deep power-down mode with typical current consumption below 1 µA. Wake-up is enabled exclusively via the dedicated WAKEUP pin (PIO0_16), which must be pulled LOW externally to exit the mode. This pin includes a 20 ns glitch filter and is independent of other interrupts or USB activity.
LPC1347FHN33,551 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 32-VQFN Exposed Pad
- Series:
- LPC13xx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 72MHz
- Connectivity:
- I2C, Microwire, SPI, SSI, SSP, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, POR, WDT
- Number of I/O:
- 26
- Program Memory Size:
- 64KB (64K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 4K x 8
- RAM Size:
- 12K x 8
- Voltage - Supply (Vcc/Vdd):
- 2V ~ 3.6V
- Data Converters:
- A/D 8x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC1347FHN33,551 FAQ
1.How can I place an order for LPC1347FHN33,551 through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC1347FHN33,551 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC1347FHN33,551 reliable?
The price and inventory of LPC1347FHN33,551 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC1347FHN33,551 is usually 5 days.
3.What payment methods are accepted for LPC1347FHN33,551?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC1347FHN33,551 transactions.
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4.How is shipping managed for LPC1347FHN33,551?
LPC1347FHN33,551 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC1347FHN33,551 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC1347FHN33,551?
For technical support, including LPC1347FHN33,551 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC1347FHN33,551 requirements.
6.How does Aetrix verify that LPC1347FHN33,551 is sourced from the original manufacturer or authorized distributors?
All LPC1347FHN33,551 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC1347FHN33,551 meets industry standards.
7.What is the process for return or replacement of LPC1347FHN33,551?
All LPC1347FHN33,551 units undergo pre-shipment inspection (PSI). If there is an issue with LPC1347FHN33,551, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC1347FHN33,551 part is unused and in its original packaging.
Return procedure for LPC1347FHN33,551:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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