NXP Semiconductors LPC1758FBD80,551
- Part No.:
- LPC1758FBD80,551
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 80-LQFP
- Datasheet:
-
LPC1758FBD80,551.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 80LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:3,885
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC1758FBD80,551 from NXP Semiconductors is a 32-bit ARM Cortex-M3 microcontroller operating at up to 100 MHz, featuring 512 kB flash, 64 kB SRAM (32 kB AHB + two 16 kB blocks), Ethernet MAC with RMII, USB 2.0 Host/Device/OTG, dual CAN 2.0B, I2S, 10-bit DAC, and 52 GPIO pins - deployed in industrial networking gateways requiring real-time protocol bridging and deterministic peripheral control.
For engineers reviewing the LPC1758FBD80,551 datasheet, LPC1758FBD80,551 pinout, LPC1758FBD80,551 application, or LPC1758FBD80,551 equivalent, key selection criteria include Ethernet+USB+CAN coexistence, 100 MHz deterministic timing, RMII interface support, DAC-enabled analog feedback, and LQFP80 package compatibility with legacy LPC17xx PCB footprints.
Technical Context
The LPC1758FBD80,551 implements an ARM Cortex-M3 core with Harvard architecture, 3-stage pipeline, and integrated MPU supporting eight memory regions. Its multilayer AHB matrix enables concurrent CPU, GPDMA, Ethernet MAC, and USB controller access without arbitration delay.
Peripheral integration includes dedicated DMA channels for Ethernet, USB, and I2S; split APB buses for low-stall CPU-DMA interaction; and pin-mapped RMII signals on Port 1 (ENET_TXD0/1, ENET_TX_EN, ENET_RXD0/1, ENET_RX_ER, ENET_REF_CLK, ENET_CRS) - all confirmed functional only on LPC1758 variants per datasheet Table 2 and Section 7.2.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M3 @ 100 MHz - delivers deterministic interrupt latency and Thumb-2 instruction efficiency for real-time control loops. |
| Memory | 512 kB flash + 64 kB SRAM (32 kB CPU-local + 16 kB Ethernet/USB/DMA + 16 kB general-purpose) - supports bootloader, protocol stacks, and buffer-intensive USB/Ethernet transfers. |
| Ethernet Interface | RMII-compliant MAC with dedicated DMA - enables 10/100 Mbps connectivity using only 7 pins and external PHY, reducing BOM vs MII. |
| USB Support | Full-speed USB 2.0 Host/Device/OTG with on-chip PHY and dedicated DMA - allows simultaneous device enumeration and host polling without CPU overhead. |
| Analog Peripherals | 12-bit ADC (6-channel, 200 kHz max) + 10-bit DAC (with dedicated timer & DMA) - enables closed-loop motor control with analog feedback and waveform generation. |
| Communication Interfaces | Dual CAN 2.0B, four UARTs (one with IrDA/RS-485), two I²C (400 kbit/s), two SSP, SPI, and I2S - supports multi-protocol industrial fieldbus bridging. |
| Package | LQFP80 (12 mm × 12 mm × 1.4 mm, SOT315-1) - provides 52 GPIOs with configurable pull-up/down, open-drain mode, and bit-banding support. |
Pinout & Package
Package: LQFP80 (plastic low-profile quad flat package, 80 leads, body size 12 mm × 12 mm × 1.4 mm, SOT315-1).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P1[0]–P1[15] | Ethernet RMII interface | ENET_TXD0/1, TX_EN, RXD0/1, RX_ER, REF_CLK, CRS - dedicated 7-pin RMII bus enabling PHY interfacing with minimal trace routing. |
| P0[29]/P0[30] | USB differential pair | USB_D+/D− - full-speed bidirectional lines with on-chip transceivers; require 27 Ω series termination per USB spec. |
| P0[26] | Analog output | AOUT - 10-bit DAC output with rail-to-rail swing; used for analog setpoint generation or audio waveform playback. |
| P0[10]/P0[11] | I²C2 interface | SDA2/SCL2 - fast-mode (400 kbit/s) I²C bus with multiple address recognition; supports sensor hub or EEPROM expansion. |
| TCK/TMS/TDO/TDI/TRST | JTAG debug interface | Standard 5-pin JTAG (IEEE 1149.1) for boundary scan, flash programming, and real-time SWO trace debugging. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated Ethernet MAC + RMII | Enables standalone 10/100 Mbps connectivity with external PHY; eliminates need for external MAC or bridge IC in gateway designs. |
| Dedicated USB PHY + OTG support | Reduces external component count by integrating full-speed transceiver and session detection logic for device/host/OTG roles. |
| Two independent CAN 2.0B controllers | Supports concurrent CANopen and J1939 network participation; each channel has dedicated message RAM and filtering. |
| I2S interface with fractional rate control | Allows precise audio sampling clock derivation from system PLL; supports 3-wire/4-wire modes for codec interfacing. |
| Motor control PWM block | Three-phase complementary outputs with dead-time insertion and fault protection inputs - suitable for BLDC/PMSM drive firmware. |
Applications
| Industrial Networking Gateway | Smart Lighting Controller |
|---|---|
Use Scenario: Protocol translation between Modbus RTU (RS-485) and EtherNet/IP over RMII Ethernet. IC Role / Device Role / Timing Role: Central protocol processor managing UART-to-Ethernet packet forwarding, real-time scheduling via NVIC, and CRC offload via hardware accelerators. Use Value: Dual CAN + dual UART + Ethernet coexistence enables fieldbus aggregation without external bridge ICs; 100 MHz core ensures sub-100 µs packet processing latency. |
Use Scenario: DALI-2 master node controlling 64 LED drivers with dimming profiles and thermal monitoring. IC Role / Device Role / Timing Role: DALI bus master with UART-based physical layer, PWM-driven LED current control, and ADC-based temperature sensing. Use Value: Four UARTs allow simultaneous DALI, debug, RS-485 commissioning, and Zigbee coexistence; 10-bit DAC generates precise reference voltages for analog dimming. |
| Energy Metering Terminal | Motor Drive Interface Module |
Use Scenario: Three-phase eMeter with pulse counting, harmonic analysis, and secure data upload via USB host to cellular modem. IC Role / Device Role / Timing Role: Metering SoC performing ADC sampling, FFT computation, RTC timestamping, and USB mass storage emulation. Use Value: 12-bit ADC with 6-channel multiplexing captures voltage/current simultaneously; USB OTG acts as removable disk for firmware updates and log export. |
Use Scenario: Inverter control board interfacing with Hall sensors, driving 3-phase IGBTs, and communicating via CAN to PLC. IC Role / Device Role / Timing Role: Motor control MCU executing FOC algorithm, generating six PWM outputs, reading quadrature encoder, and handling CAN diagnostics. Use Value: Motor control PWM block provides complementary outputs with programmable dead time; QEI interface directly tracks encoder position without CPU intervention. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC1768FBD100,551 | 100-pin LQFP, 512 kB flash, 64 kB SRAM, same peripherals but adds SD/MMC host controller and extra UART. | Required when SD card logging or additional serial interfaces are needed; incompatible pinout prevents drop-in replacement. | Select LPC1768FBD100,551 only if SDIO or pin count > 80 is mandatory; LPC1758FBD80,551 remains optimal for RMII-constrained 80-pin layouts. |
| STM32F407VGT6 | ARM Cortex-M4F @ 168 MHz, 1 MB flash, 192 kB SRAM, no native Ethernet MAC (requires external PHY + software stack), single CAN. | Suitable for DSP-heavy tasks (e.g., FFT-based power quality analysis) but lacks integrated Ethernet and dual CAN for industrial gateways. | Choose STM32F407VGT6 for floating-point math intensity; prefer LPC1758FBD80,551 when hardware-accelerated Ethernet+CAN coexistence is critical. |
Compared with LPC1768FBD100,551 and STM32F407VGT6, the LPC1758FBD80,551 uniquely balances 80-pin RMII Ethernet, dual CAN, USB OTG, and DAC in a single die - making it the most compact solution for protocol gateway applications where pin count and hardware peripheral integration are design constraints.
Availability
LPC1758FBD80,551 is available at Aetrix Electronics and suitable for industrial networking gateways, smart lighting controllers, energy metering terminals, and motor drive interface modules requiring stable component supply across multi-year production cycles.
Supply support for LPC1758FBD80,551 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in ARM-based microcontrollers and edge processing.
The LPC1758FBD80,551 belongs to the LPC17xx family - designed specifically for embedded industrial control systems demanding integrated communication peripherals (Ethernet, USB, CAN), real-time determinism, and low-power operation in harsh environments.
FAQ
What is the maximum CPU frequency supported by the LPC1758FBD80,551?
The LPC1758FBD80,551 operates at a maximum CPU frequency of 100 MHz, enabled by its ARM Cortex-M3 core and enhanced flash accelerator that delivers zero wait-state execution. This frequency is fixed for the LPC1758 variant - unlike the LPC1759 which supports 120 MHz - and is sustained across the full industrial temperature range (-40°C to +85°C) with 3.3 V ±10 % supply.
Does the LPC1758FBD80,551 include an integrated Ethernet PHY?
No, the LPC1758FBD80,551 integrates only the Ethernet MAC layer with RMII interface; it requires an external PHY such as the LAN8720A or DP83848 for physical layer connectivity. The RMII interface uses seven dedicated pins on Port 1 (ENET_TXD0/1, TX_EN, RXD0/1, RX_ER, REF_CLK, CRS) and operates at 50 MHz reference clock.
Can the LPC1758FBD80,551 support USB device and host modes simultaneously?
Yes, the LPC1758FBD80,551 supports concurrent USB device and host operation via its USB 2.0 full-speed Host/Device/OTG controller with dedicated DMA. This enables use cases like USB flash drive enumeration while acting as a CDC ACM device - verified in NXP's USBHostStack and USBDemo examples.
What is the function of the AOUT pin on the LPC1758FBD80,551?
The AOUT pin (P0[26]) is the analog output of the integrated 10-bit DAC, supporting rail-to-rail voltage output with dedicated conversion timer and DMA triggering. It is used for generating precise reference voltages, audio waveforms, or analog control signals - and is confirmed active only on LPC1758, LPC1759, LPC1756, and LPC1754 per datasheet Table 2.
Is the LPC1758FBD80,551 pin-compatible with other LPC17xx variants in LQFP80 package?
The LPC1758FBD80,551 shares the same LQFP80 footprint (SOT315-1) and core pin mapping with LPC1759FBD80, LPC1756FBD80, LPC1754FBD80, LPC1752FBD80, and LPC1751FBD80. However, peripheral pin assignments differ - notably Ethernet (P1[0]–P1[15]), I2S (P0[6]–P0[9], P4[28]–P4[29]), and DAC (P0[26]) - requiring firmware and schematic validation for cross-variant substitution.
LPC1758FBD80,551 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 80-LQFP
- Series:
- LPC17xx
- Packaging:
- Tray
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- CANbus, Ethernet, I2C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, Motor Control PWM, POR, PWM, WDT
- Number of I/O:
- 52
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 64K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.4V ~ 3.6V
- Data Converters:
- A/D 6x12b; D/A 1x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC1758FBD80,551 FAQ
1.How can I place an order for LPC1758FBD80,551 through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC1758FBD80,551 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC1758FBD80,551 reliable?
The price and inventory of LPC1758FBD80,551 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC1758FBD80,551 is usually 5 days.
3.What payment methods are accepted for LPC1758FBD80,551?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC1758FBD80,551 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC1758FBD80,551?
LPC1758FBD80,551 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC1758FBD80,551 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC1758FBD80,551?
For technical support, including LPC1758FBD80,551 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC1758FBD80,551 requirements.
6.How does Aetrix verify that LPC1758FBD80,551 is sourced from the original manufacturer or authorized distributors?
All LPC1758FBD80,551 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC1758FBD80,551 meets industry standards.
7.What is the process for return or replacement of LPC1758FBD80,551?
All LPC1758FBD80,551 units undergo pre-shipment inspection (PSI). If there is an issue with LPC1758FBD80,551, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC1758FBD80,551 part is unused and in its original packaging.
Return procedure for LPC1758FBD80,551:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC1758FBD80,551 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

