NXP Semiconductors LPC1758FBD80K
- Part No.:
- LPC1758FBD80K
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 80-LQFP
- Datasheet:
-
LPC1758FBD80K.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 80LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:595
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC1758FBD80K from NXP Semiconductors is a 32-bit ARM Cortex-M3 microcontroller operating at up to 100 MHz, featuring 512 kB flash, 64 kB SRAM (32+16+16), Ethernet MAC with RMII, USB 2.0 Host/Device/OTG, dual CAN 2.0B, I2S, 10-bit DAC, and 52 GPIO pins in an 80-pin LQFP package. It targets industrial networking and motor control systems requiring integrated connectivity and real-time analog/digital I/O.
For engineers reviewing the LPC1758FBD80K datasheet, LPC1758FBD80K pinout, LPC1758FBD80K application, or LPC1758FBD80K equivalent, key selection criteria include Ethernet + USB + dual CAN coexistence, 100 MHz deterministic execution, on-chip DMA-accelerated peripherals, and 80-pin LQFP layout compatibility with legacy LPC17xx designs.
Technical Context
The LPC1758FBD80K implements a Harvard-architecture ARM Cortex-M3 core with 3-stage pipeline, MPU supporting eight regions, and NVIC for low-latency interrupt handling. Its multilayer AHB matrix enables concurrent CPU, Ethernet MAC, USB, and GPDMA access without arbitration delay.
Peripheral integration includes dedicated DMA controllers for Ethernet (LPC1758-only), USB, and audio subsystems; split APB buses reduce CPU-DMA contention; and pin-muxing via the Pin Connect Block allows dynamic assignment of UART, SSP, I2C, CAN, PWM, ADC, and I2S functions across Port 0–2 and Port 4.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M3 with 3-stage pipeline, Harvard architecture, and MPU supporting eight memory regions. |
| Max Clock Frequency | 100 MHz - enables deterministic real-time response with zero-wait-state flash execution via integrated accelerator. |
| Memory | 512 kB flash + 64 kB SRAM (32 kB CPU-local + two 16 kB blocks for Ethernet/USB/DMA buffering). |
| Connectivity | Ethernet MAC with RMII interface, USB 2.0 full-speed Host/Device/OTG controller with on-chip PHY, dual CAN 2.0B channels. |
| Analog Peripherals | 12-bit ADC (6-channel, 200 kHz sampling) and 10-bit DAC with dedicated timer and DMA support. |
| I/O & Timing | 52 GPIO pins with configurable pull-up/down and open-drain mode; four general-purpose timers, motor control PWM, quadrature encoder interface, RTC with battery backup. |
| Package | 80-pin LQFP (12 mm × 12 mm × 1.4 mm, SOT315-1) - compatible with standard PCB assembly and thermal management for industrial environments. |
Pinout & Package
Package: 80-pin LQFP (SOT315-1), body size 12 mm × 12 mm × 1.4 mm, lead pitch 0.5 mm, RoHS-compliant plastic housing with exposed thermal pad.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0[29]/USB_D+ | USB differential data line | Bidirectional full-speed USB D+ signal; requires 90 Ω differential impedance routing and ESD protection per USB 2.0 spec. |
| P0[30]/USB_D− | USB differential data line | Bidirectional full-speed USB D− signal; paired with P0[29] for noise-immune signaling in host/device/OTG modes. |
| P1[0]/ENET_TXD0 | Ethernet transmit data bit 0 | Part of 2-bit RMII transmit bus (with P1[1]); requires controlled-impedance routing and matched trace length to ENET_TX_EN (P1[4]). |
| P1[9]/ENET_RXD0 | Ethernet receive data bit 0 | Part of 2-bit RMII receive bus (with P1[10]); routed with matched length to ENET_CRS (P1[8]) and ENET_RX_ER (P1[14]). |
| P0[26]/AOUT | DAC analog output | 10-bit voltage-output DAC channel; supports audio playback or precision analog control with external RC filtering. |
| TCK/SWDCLK | JTAG/SWD clock input | Test clock for boundary scan and Serial Wire Debug; must be driven by debugger at ≤10 MHz with clean rise/fall times. |
| RESET | Asynchronous active-low reset | 5 V tolerant, 20 ns glitch-filtered input; initiates full chip reset and forces boot ROM execution on power-up or fault recovery. |
Key Features
| Feature | Design Value |
|---|---|
| Ethernet + USB + Dual CAN Integration | Enables single-chip industrial gateway design with simultaneous wired network, USB host/device, and CAN bus communication-no external bridge ICs required. |
| GPDMA Controller | 8-channel AHB-based DMA supports memory-peripheral and memory-memory transfers; offloads CPU during high-bandwidth operations like Ethernet packet buffering or I2S audio streaming. |
| Pin Muxing Flexibility | Pin Connect Block allows runtime reassignment of peripheral functions (e.g., UART0, SSP0, I2C0) to multiple port pins-simplifies PCB layout and enables feature-scaling across product variants. |
| Low-Power Operation | Four power modes (Sleep, Deep-sleep, Power-down, Deep power-down) with wake-up via RTC, USB activity, CAN bus, or external interrupts-extends battery life in metering and sensor nodes. |
| Debug & Trace Support | Serial Wire Debug (SWD) and Serial Wire Trace (SWO) enable non-intrusive real-time instruction tracing and live register inspection without halting execution. |
Applications
| Industrial Networking Gateway | Motor Control System |
|---|---|
Use Scenario: Protocol translation between Modbus RTU over RS-485 and EtherNet/IP over RMII Ethernet in factory automation. IC Role / Device Role / Timing Role: Central MCU executing real-time protocol stacks, managing dual CAN interfaces for fieldbus bridging, and synchronizing Ethernet packet timing via hardware timers. Use Value: Eliminates need for separate Ethernet controller and CAN transceivers; 100 MHz CPU ensures sub-1 ms cycle time for motion control loops. | Use Scenario: Closed-loop three-phase BLDC motor drive with Hall-effect feedback and current sensing. IC Role / Device Role / Timing Role: Motor control PWM generator with six complementary outputs, quadrature encoder interface for position tracking, and 12-bit ADC for phase current sampling. Use Value: Integrated motor control PWM block and encoder interface reduce BOM count; DAC provides analog reference for current sense amplifiers. |
| eMetering Endpoint | Smart Lighting Controller |
Use Scenario: Electricity meter with pulse counting, tamper detection, and secure firmware updates via USB or Ethernet. IC Role / Device Role / Timing Role: Real-time data acquisition engine with RTC timestamping, 12-bit ADC for voltage/current measurement, and CRP-enabled flash security. Use Value: Battery-backed RTC ensures accurate billing timestamps during mains outage; Code Read Protection prevents unauthorized firmware extraction. | Use Scenario: DALI-2 lighting controller with dimming profiles, occupancy sensing, and remote configuration via USB. IC Role / Device Role / Timing Role: Multi-protocol interface hub managing DALI bus (via UART + isolator), analog sensor inputs (ADC), and USB device enumeration for commissioning. Use Value: Dual UARTs with RS-485 support simplify DALI physical layer; 52 GPIOs accommodate multiple LED driver enable lines and sensor interrupts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC1768FBD100 | 100-pin LQFP, 512 kB flash, 64 kB SRAM, same peripherals but adds SD/MMC host controller and extra UART. | Requires larger PCB footprint and additional SDIO routing; suited for data-logging gateways needing local storage. | Select when SD card interfacing or extra UART is required; not drop-in due to pin count and layout change. |
| LPC1778FBD100 | 100-pin LQFP, adds USB HS OTG, LCD controller, and enhanced security features; no Ethernet MAC. | Targets multimedia HMI applications; lacks Ethernet, making it unsuitable for wired industrial networking. | Choose for USB-hosted displays or secure boot applications; incompatible for Ethernet-dependent designs. |
Compared with LPC1768FBD100 and LPC1778FBD100, the LPC1758FBD80K delivers optimal balance of Ethernet + USB + dual CAN in compact 80-pin LQFP-ideal for space-constrained gateways where SDIO or LCD are unnecessary.
Availability
LPC1758FBD80K is available at Aetrix Electronics and suitable for industrial networking gateways, motor control systems, eMetering endpoints, and smart lighting controllers requiring stable component supply and long-term manufacturability.
Supply support for LPC1758FBD80K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in ARM-based microcontrollers and edge processing.
The LPC17xx family was designed for demanding embedded applications requiring rich peripheral integration, real-time determinism, and low-power operation-particularly in industrial automation, energy metering, and motor control.
FAQ
What is the maximum operating frequency of the LPC1758FBD80K?
The LPC1758FBD80K operates at a maximum CPU frequency of 100 MHz. This is achieved using the on-chip PLL, which can be driven by the main oscillator (1–25 MHz crystal), internal 4 MHz RC oscillator, or RTC oscillator. The flash accelerator enables zero-wait-state execution at this speed, ensuring deterministic real-time performance critical for industrial control loops and protocol timing.
Does the LPC1758FBD80K include an Ethernet MAC, and what interface does it support?
Yes, the LPC1758FBD80K integrates a full Ethernet MAC supporting Reduced Media Independent Interface (RMII). It includes dedicated DMA and uses pins P1[0], P1[1], P1[4], P1[8], P1[9], P1[10], P1[14], and P1[15] for RMII signals. Unlike the LPC1759, it does not support MII; RMII reduces pin count and simplifies PCB layout while maintaining 10/100 Mbps throughput for industrial Ethernet applications.
How many CAN interfaces does the LPC1758FBD80K support, and are they CAN 2.0A or 2.0B compliant?
The LPC1758FBD80K supports two CAN 2.0B-compliant controllers. Both CAN1 and CAN2 implement full CAN 2.0B specification including extended frame support (29-bit identifiers), error confinement, and automatic retransmission. CAN1 uses P0[0]/RD1 and P0[1]/TD1; CAN2 uses P2[7]/RD2 and P2[8]/TD2 - enabling dual-bus diagnostics or redundant fieldbus communication in safety-critical systems.
What analog-to-digital and digital-to-analog capabilities does the LPC1758FBD80K provide?
The LPC1758FBD80K includes a 12-bit ADC with six input channels (AD0[2]–AD0[7]), sampling up to 200 kHz, and a 10-bit DAC with dedicated conversion timer and DMA support (AOUT on P0[26]). The ADC supports burst mode and result registers for efficient data capture; the DAC provides rail-to-rail output with programmable update rate - suitable for audio playback, sensor calibration references, or analog actuator control.
Is the LPC1758FBD80K pin-compatible with other members of the LPC17xx family?
The LPC1758FBD80K shares the same 80-pin LQFP (SOT315-1) package and core pinout with LPC1751/52/54/56/59FBD80 variants, but functional pin assignments differ. For example, Ethernet pins (P1[0], P1[1], etc.) and I2S signals (P0[6]–P0[9]) are only active on LPC1758/59/56. Migration requires verification of peripheral usage and pin connect block configuration - not a direct drop-in replacement for non-Ethernet variants.
LPC1758FBD80K Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 80-LQFP
- Series:
- LPC17xx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- CANbus, Ethernet, I2C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, Motor Control PWM, POR, PWM, WDT
- Number of I/O:
- 52
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 64K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.4V ~ 3.6V
- Data Converters:
- A/D 6x12b; D/A 1x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC1758FBD80K FAQ
1.How can I place an order for LPC1758FBD80K through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC1758FBD80K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC1758FBD80K reliable?
The price and inventory of LPC1758FBD80K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC1758FBD80K is usually 5 days.
3.What payment methods are accepted for LPC1758FBD80K?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC1758FBD80K transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC1758FBD80K?
LPC1758FBD80K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC1758FBD80K order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC1758FBD80K?
For technical support, including LPC1758FBD80K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC1758FBD80K requirements.
6.How does Aetrix verify that LPC1758FBD80K is sourced from the original manufacturer or authorized distributors?
All LPC1758FBD80K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC1758FBD80K meets industry standards.
7.What is the process for return or replacement of LPC1758FBD80K?
All LPC1758FBD80K units undergo pre-shipment inspection (PSI). If there is an issue with LPC1758FBD80K, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC1758FBD80K part is unused and in its original packaging.
Return procedure for LPC1758FBD80K:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC1758FBD80K Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

