NXP Semiconductors LPC1759FBD80/P1K
- Part No.:
- LPC1759FBD80/P1K
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 80-LQFP
- Datasheet:
-
LPC1759FBD80/P1K.pdf
- Description:
- IC MCU 32BIT 512KB 80LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LPC1759FBD80/P1K from NXP Semiconductors is a 32-bit ARM Cortex-M3 microcontroller operating at up to 120 MHz, featuring 512 kB flash, 64 kB SRAM, dual CAN 2.0B interfaces, USB 2.0 Host/Device/OTG with on-chip PHY, and 52 GPIO pins - deployed in industrial motor control and networked metering systems.
For engineers reviewing the LPC1759FBD80/P1K datasheet, LPC1759FBD80/P1K pinout, LPC1759FBD80/P1K application, or LPC1759FBD80/P1K equivalent, this page delivers verified technical context, package-validated pin functions, real-world use cases, and two confirmed alternative parts for embedded design continuity.
Technical Context
The LPC1759FBD80/P1K implements an ARM Cortex-M3 core with Harvard architecture, 3-stage pipeline, and integrated MPU supporting eight memory regions. It uses separate instruction/data buses and includes a prefetch unit with speculative branching support.
Its peripheral subsystem integrates a multilayer AHB matrix interconnect enabling concurrent CPU, GPDMA, USB, and CAN access without arbitration delay; split APB buses reduce CPU-DMA stalls, while dedicated DMA channels serve USB, I2S, UART, ADC, and DAC peripherals.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M3 with NVIC, MPU (8 regions), and system tick timer - enables deterministic real-time interrupt handling and memory protection in safety-aware firmware. |
| Max Clock Frequency | 120 MHz - achieved via flash accelerator delivering zero-wait-state operation, critical for high-throughput motor control loops and USB packet processing. |
| Memory | 512 kB on-chip flash + 64 kB SRAM (32 kB CPU-local + two 16 kB AHB blocks) - supports large firmware images, Ethernet/USB buffers, and real-time data logging without external RAM. |
| Connectivity | Dual CAN 2.0B controllers, USB 2.0 Full-Speed Host/Device/OTG with on-chip PHY, four UARTs (one with RS-485/EIA-485), two I²C, two SSP, SPI, I²S - enables robust industrial fieldbus and audio interface integration. |
| Analog Peripherals | 6-channel 12-bit ADC (200 kHz max sample rate) and 10-bit DAC with dedicated timer/DMA - supports closed-loop analog sensing and actuator drive in motor and power conversion applications. |
| Timers & PWM | Four general-purpose timers (10 compare outputs), one motor-control PWM (3-phase), one quadrature encoder interface, six-output general-purpose PWM - directly implements servo drive, BLDC commutation, and position feedback. |
| Package | 80-pin LQFP (12 mm × 12 mm × 1.4 mm, SOT315-1) - provides 52 GPIOs with configurable pull-up/down, open-drain mode, and bit-banding support for fast peripheral register access. |
Pinout & Package
Package: 80-pin LQFP (SOT315-1), 12 mm × 12 mm × 1.4 mm body, lead pitch 0.5 mm, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0[26]/AOUT | DAC output | 10-bit analog voltage output (LPC1759-specific); used for precision reference generation or low-bandwidth actuator control without external DAC. |
| P0[29]/USB_D+ | USB differential pair | Full-speed USB 2.0 D+ line with integrated ESD protection; requires 27 Ω series termination per USB spec for host/device/OTG operation. |
| P0[30]/USB_D− | USB differential pair | Full-speed USB 2.0 D− line; paired with P0[29] for bidirectional communication; supports SoftConnect via P2[9]/USB_CONNECT control. |
| P1[19]/USB_PPWR | USB port power enable | Active-high signal controlling external USB VBUS switch (LPC1759-specific); enables host-mode power delivery to downstream devices. |
| P2[7]/RD2 & P2[8]/TD2 | CAN2 receiver/transmitter | Dual CAN 2.0B channel (LPC1759-specific); supports isolated bus communication in industrial networking and automotive diagnostics. |
| TCK/SWDCLK & TMS/SWDIO | Debug interface | Shared JTAG/SWD pins enabling non-intrusive Serial Wire Debug and trace; eliminates need for dedicated debug header in space-constrained designs. |
Key Features
| Feature | Design Value |
|---|---|
| Flash accelerator | Enables 120 MHz CPU operation with zero wait states - eliminates instruction fetch bottlenecks during real-time ISR execution and high-speed USB packet assembly. |
| GPDMA controller | 8-channel AHB-based DMA supporting memory-to-peripheral transfers for USB, I²S, UART, ADC, and DAC - offloads CPU from data movement, reducing latency in streaming applications. |
| I²S interface | 3- and 4-wire digital audio interface with fractional rate control and DMA support (LPC1759-specific) - enables direct connection to codecs for voice-enabled HMI or audio monitoring in smart appliances. |
| Motor control PWM | Three-phase complementary output with dead-time insertion and fault input - implements hardware-level BLDC or PMSM commutation without software timing overhead. |
| RTC with battery domain | Ultra-low-power real-time clock with 20 bytes of battery-backed registers - maintains timekeeping and event logging during main power loss in eMetering and alarm systems. |
| Power management | Four reduced-power modes (Sleep, Deep-sleep, Power-down, Deep power-down) with Wakeup Interrupt Controller - extends battery life in portable industrial sensors and remote monitoring nodes. |
Applications
| Industrial Motor Control | eMetering |
|---|---|
Use Scenario: Closed-loop speed/position control of 3-phase BLDC motors in HVAC compressors and factory automation drives. IC Role / Device Role / Timing Role: Primary MCU executing FOC algorithm, managing gate driver PWM, reading quadrature encoder feedback, and communicating via CAN bus. Use Value: Integrated motor-control PWM, quadrature encoder interface, and dual CAN enable deterministic, self-contained motor node without external timing ICs or protocol translators. |
Use Scenario: Smart electricity meter with tariff switching, tamper detection, and DLMS/COSEM over PLC or RF mesh. IC Role / Device Role / Timing Role: System-on-chip managing metrology ADC sampling, RTC-based billing intervals, secure firmware updates, and multi-protocol communication stack. Use Value: 12-bit ADC with DMA, battery-backed RTC, and dual CAN/USB support allow accurate energy accumulation, time-of-use billing, and field service connectivity in a single chip. |
| Industrial Networking | Alarm Systems |
Use Scenario: Programmable logic controller (PLC) I/O module with EtherCAT slave or CANopen master functionality. IC Role / Device Role / Timing Role: Real-time controller interfacing with digital I/O, analog inputs, and fieldbus transceivers while running deterministic cyclic tasks. Use Value: 52 GPIOs with configurable open-drain mode, dual CAN, and high-speed timers provide direct connection to industrial sensors/actuators and deterministic bus scheduling. |
Use Scenario: Fire/smoke alarm panel with multi-zone monitoring, voice alert playback, and GSM backup reporting. IC Role / Device Role / Timing Role: Central processor managing sensor polling, siren PWM output, I²S-driven audio codec, and cellular modem UART interface. Use Value: Integrated I²S, 10-bit DAC, and four UARTs with IrDA/RS-485 support eliminate external audio and interface ICs, reducing BOM count and PCB area. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC1758FBD80 | 100 MHz max CPU, no I²S or DAC, includes Ethernet MAC (RMII) | Suitable for wired industrial gateways requiring Ethernet but not audio or analog output | Select when Ethernet connectivity outweighs audio/analog generation needs and 20 MHz CPU headroom is acceptable. |
| LPC1769FBD100 | 100-pin LQFP, 512 kB flash, 64 kB SRAM, adds Ethernet MAC and USB HS device support | Targeted at higher-bandwidth gateway applications needing both Ethernet and full-speed USB device stacks | Choose for designs requiring Ethernet + USB device coexistence where larger package and extra pins are acceptable. |
Compared with LPC1759FBD80/P1K, the LPC1758FBD80 trades 20 MHz CPU speed and I²S/DAC for Ethernet capability, while the LPC1769FBD100 expands I/O and adds Ethernet at the cost of larger footprint and no DAC - making LPC1759FBD80/P1K optimal for compact, audio-capable, CAN-centric edge nodes.
Availability
LPC1759FBD80/P1K is available at Aetrix Electronics and suitable for industrial motor control, eMetering, and alarm systems requiring stable component supply across long-lifecycle production programs.
Supply support for LPC1759FBD80/P1K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in ARM-based microcontrollers and edge processing.
The LPC175x family targets resource-constrained industrial embedded systems requiring rich analog/motor/peripheral integration without external support ICs - designed specifically for deterministic real-time control in harsh environments.
FAQ
What is the maximum operating frequency of the LPC1759FBD80/P1K?
The LPC1759FBD80/P1K operates at a maximum CPU frequency of 120 MHz, enabled by its flash accelerator that delivers zero-wait-state execution. This performance level is specific to the LPC1759 variant within the LPC175x family and exceeds the 100 MHz limit of other members like the LPC1758FBD80. The 120 MHz rating is validated under 3.3 V supply and ambient temperature conditions specified in the official NXP datasheet Rev. 8.7.
Does the LPC1759FBD80/P1K include a DAC, and what is its resolution?
Yes, the LPC1759FBD80/P1K includes a 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support - a feature exclusive to the LPC1759, LPC1758, LPC1756, and LPC1754 variants. Its output appears on pin P0[26]/AOUT and is designed for low-bandwidth analog waveform generation or reference voltage synthesis in motor control and sensor calibration applications.
How many CAN interfaces does the LPC1759FBD80/P1K support?
The LPC1759FBD80/P1K supports two independent CAN 2.0B controllers, accessible via pins P0[0]/RD1/TXD3/SDA1 (CAN1) and P2[7]/RD2 & P2[8]/TD2 (CAN2). Both channels are fully functional in the LQFP80 package and enable dual-bus communication for redundancy, diagnostics, or subsystem partitioning in industrial networks and automotive test equipment.
Is the LPC1759FBD80/P1K compatible with Ethernet hardware?
No, the LPC1759FBD80/P1K does not include an Ethernet MAC or RMII interface - that capability is reserved for the LPC1758FBD80 variant only. While the LPC1759FBD80/P1K shares the same LQFP80 package and many peripherals, Ethernet-related pins (e.g., ENET_TXD0, ENET_RXD0) are not implemented or bonded out on this part, and no internal Ethernet controller logic exists.
What debug interfaces are supported by the LPC1759FBD80/P1K?
The LPC1759FBD80/P1K supports standard JTAG debugging and Serial Wire Debug (SWD) via shared pins TCK/SWDCLK, TMS/SWDIO, TDI, TDO/SWO, and TRST. It also includes an Emulation Trace Module for non-intrusive real-time instruction tracing. Boundary Scan Description Language (BSDL) is not provided for this device, and SWD is the recommended interface for modern toolchains due to its 2-pin efficiency and full debug capability.
LPC1759FBD80/P1K Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 80-LQFP
- Series:
- LPC17xx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M3
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, I2C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, Motor Control PWM, POR, PWM, WDT
- Number of I/O:
- 52
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 64K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.4V ~ 3.6V
- Data Converters:
- A/D 6x12b SAR; D/A 1x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC1759FBD80/P1K FAQ
1.How can I place an order for LPC1759FBD80/P1K through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC1759FBD80/P1K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC1759FBD80/P1K reliable?
The price and inventory of LPC1759FBD80/P1K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC1759FBD80/P1K is usually 5 days.
3.What payment methods are accepted for LPC1759FBD80/P1K?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC1759FBD80/P1K transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC1759FBD80/P1K?
LPC1759FBD80/P1K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC1759FBD80/P1K order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC1759FBD80/P1K?
For technical support, including LPC1759FBD80/P1K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC1759FBD80/P1K requirements.
6.How does Aetrix verify that LPC1759FBD80/P1K is sourced from the original manufacturer or authorized distributors?
All LPC1759FBD80/P1K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC1759FBD80/P1K meets industry standards.
7.What is the process for return or replacement of LPC1759FBD80/P1K?
All LPC1759FBD80/P1K units undergo pre-shipment inspection (PSI). If there is an issue with LPC1759FBD80/P1K, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC1759FBD80/P1K part is unused and in its original packaging.
Return procedure for LPC1759FBD80/P1K:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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