NXP Semiconductors LPC1765FBD100K
- Part No.:
- LPC1765FBD100K
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
LPC1765FBD100K.pdf
- Description:
- IC MCU 32BIT 256KB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LPC1765FBD100K from NXP Semiconductors is a 32-bit ARM Cortex-M3 microcontroller in LQFP100 package, operating at up to 100 MHz with 256 kB flash, 64 kB SRAM, dual CAN 2.0B interfaces, USB 2.0 Host/Device/OTG, and 70 GPIOs - deployed in industrial motor control, lighting systems, and white goods where deterministic real-time response and peripheral integration are critical.
For engineers reviewing the LPC1765FBD100K datasheet, LPC1765FBD100K pinout, LPC1765FBD100K application, or LPC1765FBD100K equivalent, key selection considerations include absence of Ethernet MAC, presence of I2S and DAC (LPC1765FBD100K supports both), USB OTG capability with on-chip PHY, and compatibility with LPC236x pinout for legacy migration paths.
Technical Context
The LPC1765FBD100K implements an Arm Cortex-M3 core with 3-stage pipeline, Harvard architecture, and integrated MPU supporting eight memory regions - enabling secure, deterministic execution in safety-aware embedded control. Its AHB multilayer matrix interconnect decouples CPU, GPDMA, USB, and CAN controllers to eliminate arbitration stalls during concurrent peripheral access.
Peripheral subsystems include a dedicated 8-channel GPDMA controller supporting SSP, UART, ADC, DAC, and timer match signals; dual CAN 2.0B controllers with full message RAM and acceptance filtering; and a 12-bit ADC with 8-channel multiplexing and 200 kHz sampling rate - all accessible via APB bridges with independent clock dividers for dynamic power scaling.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M3 with 3-stage pipeline, Harvard architecture, and NVIC - enables deterministic interrupt latency under 12 cycles and efficient real-time task scheduling. |
| Max Clock Frequency | 100 MHz - delivers 1.25 DMIPS/MHz performance while maintaining sub-100 µA/MHz active power efficiency. |
| Flash Memory | 256 kB on-chip flash with zero-wait-state operation at 100 MHz - supports in-system programming (ISP) and in-application programming (IAP) without external tools. |
| SRAM | 64 kB total: 32 kB AHB SRAM0 + 16 kB AHB SRAM1 + 16 kB AHB SRAM2 - enables concurrent Ethernet/USB DMA buffering and CPU instruction/data separation. |
| GPIO Count | 70 general-purpose I/O pins in LQFP100 package - all support configurable pull-up/down, open-drain mode, and Cortex-M3 bit-banding for atomic register access. |
| Communication Interfaces | 4 UARTs (1 with RS-485/EIA-485 support), 2 CAN 2.0B channels, 3 I²C-bus interfaces (1 Fast-mode Plus), 2 SSP controllers, SPI, USB 2.0 Full-Speed Host/Device/OTG - eliminates need for external protocol translators in multi-bus industrial nodes. |
| Analog Peripherals | 12-bit ADC (8 inputs, 200 kHz max sample rate) and 10-bit DAC (with dedicated timer and DMA) - enables closed-loop analog feedback and waveform generation without external converters. |
Pinout & Package
Package: LQFP100 (14 mm × 14 mm × 1.4 mm, SOT407-1); 100-pin quad flat package with exposed thermal pad, RoHS-compliant, rated for industrial temperature range (−40 °C to +85 °C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0[0]/RD1/TXD3/SDA1 | CAN1 RX / UART3 TX / I²C1 Data | Multi-function pin supporting simultaneous CAN bus reception, serial debug output, and I²C slave communication - selected via Pin Connect Block register. |
| P0[29]/USB_D+ | USB Differential Data+ | Full-speed USB 2.0 bidirectional signal routed directly to on-chip USB transceiver - requires 3.3 V tolerant IO and series 27 Ω termination per USB spec. |
| P1[0]/ENET_TXD0 | Ethernet Transmit Data 0 | Not available on LPC1765FBD100K - pin remains unused or configurable as GPIO; Ethernet MAC is disabled per Table 2 ordering options. |
| P0[26]/AD0[3]/AOUT/RXD3 | ADC Input 3 / DAC Output / UART3 RX | Dedicated DAC output (AOUT) shares pin with ADC input - enables simultaneous analog output generation and input monitoring in sensorless motor control loops. |
| P2[0]/PWM1[1]/TXD1 | PWM Channel 1 / UART1 TX | Hardware PWM output synchronized to timer base - used for LED dimming or gate drive timing; also serves as UART1 transmit path during bootloader mode. |
Key Features
| Feature | Design Value |
|---|---|
| ARM Cortex-M3 with MPU | Eight-region memory protection unit enforces privilege separation between firmware, bootloader, and application code - essential for IEC 61508 SIL2-certifiable motor drives. |
| Dual CAN 2.0B Controllers | Independent message RAM and acceptance filters per channel - supports J1939 and CANopen network stacks with zero software overhead for mailbox management. |
| USB 2.0 Full-Speed OTG | On-chip PHY and dedicated DMA enable host/device mode switching without external transceivers - reduces BOM count and PCB area in portable HMI devices. |
| 12-bit ADC + 10-bit DAC | Simultaneous sampling and waveform generation with DMA-linked buffers - eliminates CPU polling in real-time PID control loops for HVAC actuators. |
| 70 GPIO with Bit-Banding | Direct atomic read-modify-write access to individual I/O bits via Cortex-M3 bit-band alias region - guarantees race-free status flag updates in interrupt service routines. |
Applications
| Industrial Motor Control | Smart Lighting Systems |
|---|---|
Use Scenario: Closed-loop three-phase BLDC motor control with Hall-effect or encoder feedback in factory automation drives. IC Role / Device Role / Timing Role: Main system controller executing FOC algorithm, managing PWM outputs, reading ADC current/voltage samples, and communicating via CAN bus to PLC. Use Value: Integrated motor control PWM block with dead-time insertion and quadrature encoder interface eliminates external gate driver logic and position sensing ICs. | Use Scenario: DALI-2 compliant LED driver with dimming profile storage, thermal derating, and wireless commissioning via USB-CDC. IC Role / Device Role / Timing Role: System-on-chip managing DALI physical layer, PWM dimming, temperature ADC monitoring, and USB virtual COM port for configuration. Use Value: Dual CAN and USB OTG allow parallel fieldbus commissioning and local firmware update without requiring separate USB-to-serial bridge ICs. |
| White Goods Interface Module | Alarm & Security Panel |
Use Scenario: Appliance main control board interfacing with touch panel, temperature sensors, relay drivers, and cloud connectivity module. IC Role / Device Role / Timing Role: Central MCU handling user interface, sensor fusion (ADC + I²C temp/humidity), relay control (GPIO + PWM), and UART-to-WiFi bridge communication. Use Value: 70 GPIOs with configurable open-drain mode directly drive relays and interface with I²C sensors - no level shifters or buffer ICs required. | Use Scenario: Intrusion detection panel with PIR motion sensors, door contact inputs, siren PWM output, and GSM modem UART link. IC Role / Device Role / Timing Role: Real-time event processor sampling 16 zone inputs via GPIO interrupts, generating siren tone via DAC+PWM, and managing GSM AT command flow over UART1. Use Value: RTC with battery backup and 20-byte retention registers preserve alarm log timestamps across AC power loss - meets EN 50131 Grade 2 requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC1766FBD100 | Same package and pinout; 256 kB flash, 64 kB SRAM, includes Ethernet MAC - adds RMII PHY interface and associated pins. | Required where IEEE 802.3-compliant wired networking is mandatory (e.g., building BMS gateways). | Select LPC1766FBD100 only if Ethernet is needed; LPC1765FBD100K saves cost and layout complexity when CAN/USB suffice. |
| LPC1768FBD100 | Same package and pinout; 512 kB flash, 64 kB SRAM, includes Ethernet MAC and I2S - higher flash density and full peripheral set. | Suitable for feature-rich HMI with audio playback (I2S) and remote firmware updates over Ethernet. | LPC1768FBD100 offers headroom for future firmware expansion but increases BOM cost by ~18% vs. LPC1765FBD100K. |
Compared with LPC1766FBD100 and LPC1768FBD100, the LPC1765FBD100K provides optimal balance of CAN/USB connectivity, 256 kB flash, and zero Ethernet overhead - reducing PCB layer count and EMI filtering requirements in cost-sensitive industrial controls.
Availability
LPC1765FBD100K is available at Aetrix Electronics and suitable for industrial motor control, smart lighting systems, and white goods requiring stable component supply with long-term manufacturing continuity and full traceability.
Supply support for LPC1765FBD100K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader headquartered in Eindhoven, Netherlands, delivering secure, scalable solutions for automotive, industrial, IoT, and mobile applications.
The LPC176x family was designed specifically for real-time industrial control - emphasizing deterministic interrupt response, integrated analog peripherals, and robust communication stacks (CAN, USB, I²C) without external co-processors.
FAQ
What is the maximum operating frequency of the LPC1765FBD100K?
The LPC1765FBD100K operates at a maximum CPU frequency of 100 MHz, achieved using its internal PLL driven by the main oscillator (1–25 MHz crystal) or 4 MHz internal RC oscillator. This frequency is sustained with zero wait states in flash memory due to the integrated flash accelerator, enabling consistent 1.25 DMIPS/MHz performance for time-critical control tasks.
Does the LPC1765FBD100K include an Ethernet MAC?
No, the LPC1765FBD100K does not include an Ethernet MAC. As confirmed in Table 2 of the official NXP datasheet (Rev. 9.10), "Ethernet" is marked "no" for LPC1765FBD100. Pins reserved for Ethernet functions (e.g., ENET_TXD0, ENET_RXD0) are unconnected internally and must be treated as GPIO or left floating in PCB layout.
Which communication interfaces are supported by the LPC1765FBD100K?
The LPC1765FBD100K supports four UARTs (one with RS-485/EIA-485 support), two CAN 2.0B controllers, three I²C-bus interfaces (including one Fast-mode Plus capable of 1 Mbit/s), two SSP controllers, SPI, and USB 2.0 Full-Speed Host/Device/OTG with on-chip PHY - all accessible via dedicated DMA channels for zero-CPU-overhead data transfer.
Is the LPC1765FBD100K pin-compatible with other LPC176x variants?
Yes, the LPC1765FBD100K is fully pin-compatible with all LQFP100-packaged LPC176x devices (e.g., LPC1766FBD100, LPC1768FBD100) and maintains mechanical and electrical compatibility with the legacy LPC236x Arm7 series - enabling drop-in replacement in existing designs where Ethernet is not required.
What analog peripherals are integrated into the LPC1765FBD100K?
The LPC1765FBD100K integrates a 12-bit Analog-to-Digital Converter (ADC) with eight input channels and 200 kHz maximum sample rate, plus a 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support - both accessible through shared GPIO pins (e.g., P0[26] for AOUT/AD0[3]) and usable concurrently in closed-loop control applications.
LPC1765FBD100K Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 100-LQFP
- Series:
- LPC17xx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- CANbus, I2C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, Motor Control PWM, POR, PWM, WDT
- Number of I/O:
- 70
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 64K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.4V ~ 3.6V
- Data Converters:
- A/D 8x12b; D/A 1x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC1765FBD100K FAQ
1.How can I place an order for LPC1765FBD100K through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC1765FBD100K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC1765FBD100K reliable?
The price and inventory of LPC1765FBD100K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC1765FBD100K is usually 5 days.
3.What payment methods are accepted for LPC1765FBD100K?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC1765FBD100K transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC1765FBD100K?
LPC1765FBD100K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC1765FBD100K order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC1765FBD100K?
For technical support, including LPC1765FBD100K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC1765FBD100K requirements.
6.How does Aetrix verify that LPC1765FBD100K is sourced from the original manufacturer or authorized distributors?
All LPC1765FBD100K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC1765FBD100K meets industry standards.
7.What is the process for return or replacement of LPC1765FBD100K?
All LPC1765FBD100K units undergo pre-shipment inspection (PSI). If there is an issue with LPC1765FBD100K, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC1765FBD100K part is unused and in its original packaging.
Return procedure for LPC1765FBD100K:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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