NXP Semiconductors LPC1765FET100K

Overview

LPC1765FET100K from NXP Semiconductors is a 32-bit ARM Cortex-M3 microcontroller in TFBGA100 package, operating at up to 100 MHz with 256 kB flash, 64 kB SRAM, dual CAN 2.0B interfaces, USB 2.0 Host/Device/OTG, and 70 GPIOs - deployed in industrial motor control, white goods, and lighting systems requiring real-time I/O and protocol flexibility.

For engineers reviewing the LPC1765FET100K datasheet, LPC1765FET100K pinout, LPC1765FET100K application, or LPC1765FET100K equivalent, key selection considerations include its TFBGA100 footprint, absence of Ethernet MAC, DAC availability, I2S support, and compatibility with LPC236x Arm7-based designs for legacy migration paths.

Technical Context

The LPC1765FET100K implements a Harvard-architecture Cortex-M3 core with 3-stage pipeline, integrated MPU supporting eight memory regions, and NVIC for deterministic interrupt handling. Its AHB multilayer matrix enables concurrent CPU, DMA, USB, and CAN access without arbitration delay.

Peripheral subsystems include a 12-bit ADC (8-channel, 200 kHz sampling), 10-bit DAC (dedicated timer + DMA), four general-purpose timers (eight capture inputs, ten compare outputs), and motor control PWM with three-phase support - all accessible via configurable pin-muxing through the Pin Connect Block.

Key Specifications

Pinout & Package

Package: TFBGA100 (plastic thin fine-pitch ball grid array; 100 balls; body 9 mm × 9 mm × 0.7 mm; SOT926-1).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microcontroller applications.

Compared with LPC1766FBD100, the LPC1765FET100K saves board space via TFBGA and removes Ethernet overhead; versus LPC1768FET100, it trades flash capacity for lower unit cost while retaining identical I/O, USB, and CAN functionality for established firmware footprints.

Availability

LPC1765FET100K is available at Aetrix Electronics and suitable for industrial motor control, smart lighting systems, and white goods applications requiring stable component supply, long-term manufacturability, and RoHS-compliant packaging.

Supply support for LPC1765FET100K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in ARM-based microcontrollers and edge processing.

The LPC176x series was designed for cost-sensitive, high-integration embedded applications demanding real-time responsiveness, mixed-signal capability, and industrial-grade reliability - targeting motor control, human-machine interface, and protocol gateway use cases.

FAQ

Does the LPC1765FET100K include an Ethernet MAC?

No, the LPC1765FET100K does not include an Ethernet MAC. As confirmed in Table 2 of the official NXP datasheet (Rev. 9.10), Ethernet is explicitly marked "no" for this variant. Pins such as P1[0]/ENET_TXD0 and P1[4]/ENET_TX_EN are present but unconnected to internal Ethernet logic and must be configured as GPIO or alternate peripherals via the Pin Connect Block. The LPC1765FET100K retains full USB 2.0 Host/Device/OTG and dual CAN 2.0B functionality.

What is the maximum operating frequency of the LPC1765FET100K?

The LPC1765FET100K operates at a maximum CPU frequency of 100 MHz, as specified in Table 2 and Section 2 of the NXP datasheet. This is achieved using the on-chip PLL, which can be driven by the main oscillator (1–25 MHz crystal), internal 4 MHz RC oscillator, or RTC oscillator. The 100 MHz rating applies across the full industrial temperature range (−40 °C to +85 °C) under 3.3 V ±10 % supply conditions.

Is the DAC available on the LPC1765FET100K?

Yes, the LPC1765FET100K includes a 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support, as confirmed in Table 2 ("DAC: yes") and Section 2 features list. The DAC output is available on pin P0[26]/AOUT. It supports continuous waveform generation and analog actuator control, and is functionally identical to the DAC in LPC1768/LPC1769 variants.

What debug interfaces does the LPC1765FET100K support?

The LPC1765FET100K supports JTAG debug interface (standard IEEE 1149.1) for full boundary scan and emulation, plus Serial Wire Debug (SWD) and Serial Wire Trace (SWO) for non-intrusive real-time instruction tracing. SWD uses only two pins (SWDIO and SWCLK), reducing debug footprint versus JTAG. Boundary Scan Description Language (BSDL) is not provided for this device, per datasheet Section 2.

How many GPIO pins are available on the LPC1765FET100K?

Up to 70 general-purpose I/O pins are available on the LPC1765FET100K, as stated in Section 1 and Table 2 of the datasheet. These are distributed across Ports 0–4, with all GPIOs supporting configurable pull-up/down resistors and a new open-drain operating mode. Pin availability depends on peripheral multiplexing - for example, P0[27] and P0[28] serve dual I²C0/USB roles, but remain usable as GPIO when those functions are disabled.