My Inquiry
My Account
NXP Semiconductors LPC1767FBD100K
- Part No.:
- LPC1767FBD100K
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
LPC1767FBD100K.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 100LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:3,916
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC1767FBD100K from NXP Semiconductors is a 32-bit ARM Cortex-M3 microcontroller in LQFP100 package, operating at up to 100 MHz with 512 kB flash, 64 kB SRAM, Ethernet MAC, and dual CAN 2.0B controllers-designed for industrial networking and motor control systems requiring real-time I/O, deterministic timing, and protocol stack integration.
For engineers reviewing the LPC1767FBD100K datasheet, LPC1767FBD100K pinout, LPC1767FBD100K application, or LPC1767FBD100K equivalent, key selection criteria include its 100 MHz CPU frequency, 70 GPIO pins with configurable open-drain mode, absence of USB Host/OTG and I2S interfaces (per Table 2), and compatibility with LPC236x pinout for legacy migration paths.
Technical Context
The LPC1767FBD100K implements an Arm Cortex-M3 core with Harvard architecture, 3-stage pipeline, and integrated Memory Protection Unit (MPU) supporting eight memory regions. Its AHB multilayer matrix enables concurrent access by CPU, GPDMA, Ethernet MAC, and USB peripherals without arbitration delay.
Peripheral subsystems include a 12-bit ADC (8-channel, 200 kHz sampling), 10-bit DAC (available on this variant), four general-purpose timers with capture/compare, motor control PWM, quadrature encoder interface, RTC with battery backup, and Wake-up Interrupt Controller (WIC) for low-power mode recovery via external interrupts or CAN activity.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M3 with MPU, enabling secure memory partitioning for RTOS and safety-critical tasks. |
| Max Clock Frequency | 100 MHz - supports real-time deterministic execution for motor control loops and industrial communication stacks. |
| Flash / SRAM | 512 kB flash + 64 kB SRAM (32 kB AHB SRAM0 + 16 kB AHB SRAM1 + 16 kB AHB SRAM2) - sufficient for dual-bank firmware updates and Ethernet buffer allocation. |
| GPIO Count | 70 pins with configurable pull-up/down and open-drain mode - enables direct interfacing with RS-485 transceivers, optocouplers, and industrial sensors. |
| Communication Peripherals | Ethernet MAC (RMII), 4× UART (with IrDA/RS-485 support), 2× CAN 2.0B, 3× I²C, 2× SSP, SPI - meets requirements for fieldbus gateway and distributed I/O node designs. |
| Analog Peripherals | 12-bit ADC (8 inputs, 200 kHz), 10-bit DAC (single output) - supports closed-loop analog feedback and waveform generation in motor drive applications. |
| Power Modes | Four reduced-power modes (Sleep, Deep-sleep, Power-down, Deep power-down) with WIC wake-up - extends battery life in remote monitoring nodes. |
Pinout & Package
Package: LQFP100 (14 mm × 14 mm × 1.4 mm, SOT407-1). 100-pin quad flat package with exposed thermal pad, compatible with standard reflow profiles and manual soldering.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0[0]–P0[31] | General-purpose I/O port 0 | 32-bit bidirectional port with individual direction control; supports bit-banding and DMA access via AHB bus. |
| P1[0]–P1[31] | General-purpose I/O port 1 | 32-bit port with Ethernet TX/RX signals (ENET_TXD0/1, ENET_RXD0/1) and USB D+/D− on select pins. |
| P2[0]–P2[13] | General-purpose I/O port 2 | 14-bit port including EINT0–EINT3, PWM1 outputs, and trace debug signals (TRACEDATA[0–3], TRACECLK). |
| P3[25]–P3[26] | Timer/PWM extension | MAT0[0]/MAT0[1] and STCLK - used for precise timing synchronization and system clock distribution. |
| P4[28]–P4[29] | Auxiliary I/O | RX_MCLK/TX_MCLK - I²S master clock inputs for audio codec interfacing (not functional on LPC1767FBD100K per Table 2). |
Key Features
| Feature | Design Value |
|---|---|
| Pin-compatible with LPC236x | Enables drop-in replacement in legacy ARM7-based designs without PCB revision. |
| Dual CAN 2.0B controllers | Supports J1939 and CANopen protocols simultaneously for vehicle diagnostics and industrial automation networks. |
| Ethernet MAC with RMII | Reduces external component count by eliminating PHY need in basic Ethernet connectivity applications. |
| Configurable open-drain GPIO | Eliminates external pull-up resistors for I²C/SMBus and wired-AND logic in multi-master systems. |
| Wake-up Interrupt Controller (WIC) | Allows CPU resume from Power-down mode within 1 µs upon CAN frame reception or external interrupt edge. |
Applications
| Industrial Networking Gateway | Motor Control Drive |
|---|---|
Use Scenario: Protocol translation between Modbus RTU (RS-485) and EtherNet/IP over embedded switch. IC Role / Device Role / Timing Role: Central MCU executing dual-stack firmware, managing packet buffering, CRC validation, and timestamped event logging. Use Value: 70 GPIO pins enable direct RS-485 transceiver control; Ethernet MAC + dual CAN allow concurrent fieldbus and backbone network operation. | Use Scenario: Closed-loop servo drive for HVAC compressors using FOC algorithm and Hall-effect feedback. IC Role / Device Role / Timing Role: Real-time controller executing PWM generation, ADC sampling, and PID computation at 20 kHz loop rate. Use Value: Motor control PWM block delivers six complementary outputs with dead-time insertion; 12-bit ADC samples current sensors at 200 kHz for accurate torque regulation. |
| Smart Energy Meter | Alarm System Controller |
Use Scenario: DIN-rail mounted meter with pulse counting, tariff switching, and HAN communication via PLC or RF. IC Role / Device Role / Timing Role: Main processor handling metrology calculations, secure firmware updates, and tamper detection logic. Use Value: RTC with 20-byte battery-backed registers stores time-of-use data during mains failure; 10-bit DAC generates reference voltages for analog front-end calibration. | Use Scenario: Panel-mounted intrusion detection hub connecting PIR, door contact, and siren outputs across 16 zones. IC Role / Device Role / Timing Role: Supervisory controller managing sensor polling, alarm escalation, and GSM modem handshaking. Use Value: Four external interrupt inputs (EINT0–EINT3) support immediate response to zone triggers; WIC wakes CPU from Deep power-down on motion detection. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC1768FBD100 | Includes USB Device/Host/OTG controller and I²S interface; otherwise identical flash/SRAM/peripheral set. | Required for USB peripheral device firmware updates or audio streaming; not needed for pure CAN/Ethernet gateways. | Select LPC1768FBD100 only if USB host capability or I²S audio path is mandatory. |
| LPC1766FBD100 | Same package and pinout, but reduced flash (256 kB); retains Ethernet, dual CAN, and all analog peripherals. | Suitable for cost-sensitive applications where firmware footprint fits within 256 kB and no future feature expansion is planned. | Choose LPC1766FBD100 when BOM cost reduction is critical and code size remains under 256 kB. |
Compared with LPC1768FBD100, LPC1767FBD100K omits USB OTG and I²S to reduce silicon area and cost while retaining full Ethernet/CAN functionality; versus LPC1766FBD100, it doubles flash capacity to 512 kB for complex protocol stacks and field-upgradable firmware.
Availability
LPC1767FBD100K is available at Aetrix Electronics and suitable for industrial networking gateways, motor control drives, smart energy meters, and alarm system controllers requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.
Supply support for LPC1767FBD100K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with headquarters in Eindhoven, Netherlands.
The LPC176x series was designed specifically for real-time industrial control applications demanding high peripheral integration, deterministic interrupt latency, and seamless migration from ARM7-based platforms like the LPC236x family.
FAQ
What is the maximum operating frequency of the LPC1767FBD100K?
The LPC1767FBD100K operates at a maximum CPU frequency of 100 MHz, achieved via internal PLL driven by the main oscillator, internal RC oscillator, or RTC oscillator. This frequency is confirmed in Table 2 of the official NXP datasheet Rev. 9.10 and enables deterministic execution of real-time control algorithms in motor drive and industrial automation applications. The LPC1767FBD100K does not support the 120 MHz mode found in the LPC1769 variant.
Does the LPC1767FBD100K include USB Host/OTG functionality?
No, the LPC1767FBD100K does not include USB Host/OTG functionality. As specified in Table 2 of the NXP datasheet Rev. 9.10, USB capability is marked "no" for this part number, distinguishing it from the LPC1768FBD100 and LPC1769FBD100 variants. The LPC1767FBD100K retains USB Device-only mode, which supports firmware updates and HID-class peripherals but excludes host enumeration or OTG role switching.
How many CAN controllers are integrated into the LPC1767FBD100K?
The LPC1767FBD100K integrates two CAN 2.0B controllers, as explicitly stated in both the General Description section and Table 2 of the NXP datasheet Rev. 9.10. These controllers support full CAN protocol compliance, including identifier masking, message filtering, and FIFO-based transmission/reception-making the LPC1767FBD100K suitable for J1939-based vehicle diagnostics and CANopen industrial networks.
What package type is used for the LPC1767FBD100K?
The LPC1767FBD100K uses the LQFP100 package (plastic low-profile quad flat package with 100 leads, body size 14 mm × 14 mm × 1.4 mm, SOT407-1). This package is pin-compatible with the LPC236x series and supports standard surface-mount assembly processes, including reflow soldering and automated optical inspection. Pin configuration details are provided in Figure 2 and Table 5 of the NXP datasheet.
Is the LPC1767FBD100K pin-compatible with the LPC236x microcontroller family?
Yes, the LPC1767FBD100K is pin-compatible with the 100-pin LPC236x ARM7-based microcontroller series, as confirmed in the General Description section of the NXP datasheet Rev. 9.10. This compatibility allows direct PCB-level replacement in existing designs, preserving layout, routing, and external circuitry while upgrading to the higher-performance ARM Cortex-M3 architecture, enhanced debug features, and expanded peripheral set of the LPC1767FBD100K.
LPC1767FBD100K Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 100-LQFP
- Series:
- LPC17xx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- I2C, IrDA, Microwire, SPI, SSI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, Motor Control PWM, POR, PWM, WDT
- Number of I/O:
- 70
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 64K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.4V ~ 3.6V
- Data Converters:
- A/D 8x12b; D/A 1x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC1767FBD100K FAQ
1.How can I place an order for LPC1767FBD100K through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC1767FBD100K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC1767FBD100K reliable?
The price and inventory of LPC1767FBD100K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC1767FBD100K is usually 5 days.
3.What payment methods are accepted for LPC1767FBD100K?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC1767FBD100K transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC1767FBD100K?
LPC1767FBD100K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC1767FBD100K order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC1767FBD100K?
For technical support, including LPC1767FBD100K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC1767FBD100K requirements.
6.How does Aetrix verify that LPC1767FBD100K is sourced from the original manufacturer or authorized distributors?
All LPC1767FBD100K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC1767FBD100K meets industry standards.
7.What is the process for return or replacement of LPC1767FBD100K?
All LPC1767FBD100K units undergo pre-shipment inspection (PSI). If there is an issue with LPC1767FBD100K, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC1767FBD100K part is unused and in its original packaging.
Return procedure for LPC1767FBD100K:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC1767FBD100K Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
