NXP Semiconductors LPC2105BBD48,151
- Part No.:
- LPC2105BBD48,151
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 48-LQFP
- Datasheet:
-
LPC2105BBD48,151.pdf
- Description:
- IC MCU 16/32B 128KB FLASH 48LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LPC2105BBD48,151 from NXP Semiconductors is a 32-bit ARM7TDMI-S microcontroller in LQFP48 package, featuring 128 kB flash, 32 kB on-chip SRAM, dual UARTs with fractional baud rate generators, two 32-bit timers (7 capture/compare channels), six PWM outputs, and 32 GPIO pins with 5 V tolerance - deployed in industrial control, protocol converters, and access control systems.
For engineers reviewing the LPC2105BBD48,151 datasheet, LPC2105BBD48,151 pinout, LPC2105BBD48,151 application, or LPC2105BBD48,151 equivalent, key selection criteria include its 60 MHz CPU clock, dual UART hardware flow control, 32-bit timer resolution, 5 V tolerant I/O voltage range (3.0–3.6 V), and support for In-System Programming (ISP) and In-Application Programming (IAP).
Technical Context
The LPC2105BBD48,151 implements an ARM7TDMI-S core with Thumb instruction set support, enabling 32-bit code execution at 60 MHz via a 128-bit wide memory interface and accelerator architecture. Its Vectored Interrupt Controller (VIC) supports configurable priorities across 16 vectored IRQ slots and FIQ/IRQ/non-vectored classification.
Peripherals include two UARTs (16C550-compatible) with autobauding and hardware handshake, Fast I²C-bus (400 kbit/s), SPI/SSP controller, Real-Time Clock, Watchdog, and a PWM unit with six independent outputs - all accessible through multiplexed GPIO pins managed by the Pin Connect Block.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM7TDMI-S 32-bit RISC processor with Thumb mode for 30 % smaller code size and minimal performance penalty. |
| Max Clock Speed | 60 MHz via programmable on-chip PLL with 100 µs settling time - enables real-time deterministic timing for control loops. |
| Flash Memory | 128 kB ISP/IAP flash with 100,000 erase/write cycles and 20-year data retention - supports field firmware updates without external programmer. |
| SRAM | 32 kB on-chip static RAM accessible as 8/16/32-bit - sufficient for real-time buffers in soft modem or voice recognition applications. |
| I/O Voltage | 5 V tolerant GPIO (3.0–3.6 V I/O supply, 1.65–1.95 V core) - simplifies level-shifting in mixed-voltage industrial interfaces. |
| Timers & PWM | Two 32-bit general-purpose timers (7 capture/compare channels total) and 6-channel PWM unit - suitable for motor control and LED dimming with precise duty-cycle resolution. |
| Serial Interfaces | Dual UARTs (fractional baud rate, hardware flow control), Fast I²C (400 kbit/s), SPI/SSP - enables multi-protocol gateway design without external transceivers. |
Pinout & Package
Package: LQFP48 (7 mm × 7 mm × 1.4 mm, SOT313-2), 48-pin plastic low-profile quad flat package with 32 GPIO pins (P0.0–P0.31), dual power domains (VDD(1V8), VDD(3V3)), and dedicated JTAG/trace pins.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0.0/TXD0/PWM1 | UART 0 transmit / PWM output 1 | Primary serial debug channel or PWM signal source; open-drain capable when configured for I²C functions. |
| P0.1/RXD0/PWM3 | UART 0 receive / PWM output 3 | Full-duplex UART 0 interface or auxiliary PWM output; supports TTL-level input with hysteresis. |
| P0.2/SCL/CAP0.0 | I²C clock / Timer 0 capture input | Open-drain I²C-bus clock line or edge-triggered event counter input for high-precision timing. |
| P0.3/SDA/MAT0.0 | I²C data / Timer 0 match output | Open-drain I²C-bus data line or programmable pulse generator for periodic interrupts or waveform synthesis. |
| RESET | Active-low reset input | TTL-compatible, 5 V tolerant reset pin with hysteresis - ensures reliable power-on and brown-out recovery. |
| VDD(1V8) | Core power supply | 1.8 V ± 8.3 % supply for ARM7TDMI-S core and internal logic - requires low-noise regulation for stable 60 MHz operation. |
| VDD(3V3) | I/O power supply | 3.3 V ± 10 % supply for all GPIO and peripheral I/O - enables direct interfacing with 3.3 V logic and 5 V tolerant operation. |
Key Features
| Feature | Design Value |
|---|---|
| Fast GPIO port | Port pin toggle up to 3.5× faster than legacy LPC210x; allows real-time bit-banging and simultaneous read of any pin regardless of function. |
| Fractional baud rate UARTs | UART 0/1 support precise non-integer baud rates (e.g., 115200, 921600) without external crystal changes - critical for interoperability with legacy modems. |
| Hardware flow control | RTS/CTS/DSR/DTR/DCD/RI signals fully implemented in UART 1 hardware - eliminates software overhead in high-throughput serial gateways. |
| Embedded Trace Macrocell | Non-intrusive real-time instruction trace via TRACECLK, TRACESYNC, and four TRACEPKT lines - enables cycle-accurate debugging without halting CPU. |
| Diversified Code Read Protection | Multiple CRP levels prevent unauthorized flash readout while allowing selective debug access - meets basic firmware security requirements for OEM deployments. |
Applications
| Industrial Control | Protocol Converter |
|---|---|
Use Scenario: PLC I/O expansion module requiring deterministic response to sensor inputs and actuator commands. IC Role / Device Role / Timing Role: Central controller executing real-time control algorithms using 32-bit timers and PWM outputs for servo drive modulation. Use Value: 60 MHz ARM7TDMI-S core with VIC interrupt prioritization ensures sub-100 µs response to emergency stop signals. | Use Scenario: RS-232 to Modbus RTU bridge connecting legacy instrumentation to Ethernet-based SCADA systems. IC Role / Device Role / Timing Role: Protocol translation engine managing dual UARTs with hardware flow control and buffer management in 32 kB SRAM. Use Value: Fractional baud rate generation and autobauding enable plug-and-play compatibility with diverse field devices operating at non-standard rates. |
| Access Control Terminal | Voice Recognition Front-End |
Use Scenario: Compact biometric door controller integrating fingerprint sensor, RFID reader, and relay driver. IC Role / Device Role / Timing Role: Low-power host MCU handling secure authentication, GPIO-driven peripherals, and watchdog supervision. Use Value: Dual power domains (1.8 V core / 3.3 V I/O) and Idle/Power-down modes reduce active current to <1 mA during standby. | Use Scenario: Edge device preprocessing audio samples before sending feature vectors to cloud AI service. IC Role / Device Role / Timing Role: Signal acquisition node using I²C-connected ADC and SPI-connected flash for local buffering. Use Value: 32 kB SRAM provides >2 seconds of 16-bit mono audio at 8 kHz sampling - sufficient for keyword spotting without external memory. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC2106BBD48 | 64 kB SRAM vs. 32 kB; identical flash, package, peripherals, and clock specs. | Better suited for applications requiring larger firmware images or extended audio/data buffers. | Select LPC2106BBD48 when >32 kB RAM is needed for complex protocol stacks or real-time DSP buffers. |
| LPC2138FBD64 | 64-pin LQFP, 512 kB flash, 32 kB SRAM, USB 2.0 Device, 10-bit ADC - not pin-compatible. | Supports USB connectivity and higher-resolution analog sensing; targets more feature-rich embedded systems. | Choose LPC2138FBD64 only when USB host/device capability or integrated ADC is required - requires PCB redesign. |
Compared with LPC2105BBD48,151, LPC2106BBD48 offers double the SRAM for larger runtime workloads without changing layout, while LPC2138FBD64 adds USB and ADC but demands new footprint and firmware adaptation - making LPC2105BBD48,151 optimal for cost-sensitive, compact UART/I²C gateway designs.
Availability
LPC2105BBD48,151 is available at Aetrix Electronics and suitable for industrial control, access control terminals, and protocol converter applications requiring stable component supply, long-term lifecycle support, and verified 5 V tolerant I/O operation.
Supply support for LPC2105BBD48,151 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company delivering high-performance mixed-signal and RF solutions for automotive, industrial, and IoT markets.
The LPC2100 series was designed as a cost-optimized, low-power 32-bit microcontroller family targeting compact embedded systems where small footprint, deterministic real-time response, and multi-protocol serial connectivity are essential - exemplified by LPC2105BBD48,151.
FAQ
What is the maximum operating frequency of the LPC2105BBD48,151?
The LPC2105BBD48,151 achieves a maximum CPU clock frequency of 60 MHz using its on-chip Phase-Locked Loop (PLL) with 100 µs settling time. This frequency is sustained via a 128-bit wide memory interface and accelerator architecture that enables full-speed 32-bit code execution - confirmed in the official NXP datasheet Rev. 07.
Does the LPC2105BBD48,151 support In-System Programming (ISP)?
Yes, the LPC2105BBD48,151 supports In-System Programming via its UART0 interface using the on-chip bootloader. Flash programming takes 1 ms per 512-byte line, and sector or full-chip erase completes in 400 ms - enabling field firmware updates without removing the LPC2105BBD48,151 from the target board.
How much SRAM does the LPC2105BBD48,151 have, and what is its access width?
The LPC2105BBD48,151 integrates 32 kB of on-chip static RAM accessible as 8-bit, 16-bit, or 32-bit words. This SRAM is mapped into the ARM7TDMI-S memory space and supports zero-wait-state operation at 60 MHz - providing ample buffer space for communication protocols and real-time data processing within the LPC2105BBD48,151.
Are the GPIO pins on the LPC2105BBD48,151 5 V tolerant?
Yes, all 32 GPIO pins (P0.0–P0.31) on the LPC2105BBD48,151 are 5 V tolerant with TTL input levels and hysteresis. They operate with a 3.0–3.6 V I/O supply (VDD(3V3)) and support 10 ns slew rate control - allowing direct interfacing with 5 V logic without external level shifters.
What debug interfaces does the LPC2105BBD48,151 provide?
The LPC2105BBD48,151 provides JTAG (IEEE 1149.1) via primary and secondary pin groups (TCK/TMS/TDI/TDO/TRST), EmbeddedICE-RT for breakpoints and watchpoints, and an Embedded Trace Macrocell (ETM) for non-intrusive real-time instruction tracing - all supported natively by the ARM7TDMI-S core inside the LPC2105BBD48,151.
LPC2105BBD48,151 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 48-LQFP
- Series:
- LPC2100
- Packaging:
- Bag
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- ARM7®
- Core Size:
- 16/32-Bit
- Speed:
- 60MHz
- Connectivity:
- I2C, Microwire, SPI, SSI, SSP, UART/USART
- Peripherals:
- POR, PWM, WDT
- Number of I/O:
- 32
- Program Memory Size:
- 128KB (128K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 32K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.65V ~ 3.6V
- Data Converters:
- -
- Oscillator Type:
- Internal
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC2105BBD48,151 FAQ
1.How can I place an order for LPC2105BBD48,151 through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC2105BBD48,151 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC2105BBD48,151 reliable?
The price and inventory of LPC2105BBD48,151 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC2105BBD48,151 is usually 5 days.
3.What payment methods are accepted for LPC2105BBD48,151?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC2105BBD48,151 transactions.
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4.How is shipping managed for LPC2105BBD48,151?
LPC2105BBD48,151 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC2105BBD48,151 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC2105BBD48,151?
For technical support, including LPC2105BBD48,151 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC2105BBD48,151 requirements.
6.How does Aetrix verify that LPC2105BBD48,151 is sourced from the original manufacturer or authorized distributors?
All LPC2105BBD48,151 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC2105BBD48,151 meets industry standards.
7.What is the process for return or replacement of LPC2105BBD48,151?
All LPC2105BBD48,151 units undergo pre-shipment inspection (PSI). If there is an issue with LPC2105BBD48,151, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC2105BBD48,151 part is unused and in its original packaging.
Return procedure for LPC2105BBD48,151:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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