NXP Semiconductors LPC2106FHN48/01,55
- Part No.:
- LPC2106FHN48/01,55
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
LPC2106FHN48/01,55.pdf
- Description:
- IC MCU 16/32B 128KB FLSH 48HVQFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,659
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Product details
Overview
LPC2106FHN48/01 from NXP Semiconductors is a 32-bit ARM7TDMI-S microcontroller with 128 kB flash, 64 kB SRAM, 60 MHz max CPU clock, 32 GPIO pins (5 V tolerant), and dual UARTs with fractional baud rate generators. It integrates PWM, timers, I²C, SPI/SSP, RTC, watchdog, and embedded trace support - deployed in industrial control, protocol converters, and low-end imaging systems.
For engineers reviewing the LPC2106FHN48/01 datasheet, LPC2106FHN48/01 pinout, LPC2106FHN48/01 application, or LPC2106FHN48/01 equivalent, key selection criteria include its HVQFN48 thermal-enhanced package, −40 °C to +85 °C industrial temperature range, dual power domains (1.8 V core / 3.3 V I/O), and JTAG/trace debug capability with TRST/TMS/TCK/TDI/TDO on primary and secondary pin groups.
Technical Context
The LPC2106FHN48/01 implements the ARM7TDMI-S RISC core with Thumb instruction set for code density optimization, enabling up to 65 % smaller footprint versus ARM mode while retaining >160 % performance of a 16-bit processor on 16-bit memory. Its 128-bit-wide flash interface and accelerator deliver full 60 MHz execution without wait states.
It features a Vectored Interrupt Controller (VIC) supporting FIQ/vectored/non-vectored IRQs, two 32-bit timers (7 capture/compare channels), six PWM outputs, and Fast GPIO enabling port pin toggling up to 3.5× faster than earlier variants - all accessible via a unified 32-bit peripheral register map over AMBA AHB/APB buses.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM7TDMI-S 32-bit RISC processor with Thumb mode for compact, high-efficiency firmware. |
| Max Clock Speed | 60 MHz via on-chip PLL (100 µs settling time); supports 1–25 MHz crystal input. |
| Memory | 128 kB ISP/IAP flash (100k erase/write cycles, 20-year retention); 64 kB on-chip SRAM. |
| I/O Voltage | Dual supply: 1.65–1.95 V (1.8 V ±8.3 %) core; 3.0–3.6 V (3.3 V ±10 %) I/O with 5 V tolerant pins. |
| Peripherals | 2 × UART (16C550-compatible, fractional baud, hardware flow control); I²C (400 kbit/s); SPI/SSP; 2 × 32-bit timers; 6-channel PWM; RTC; watchdog. |
| Debug & Trace | EmbeddedICE-RT interface with breakpoints/watchpoints; Embedded Trace Macrocell (ETM) with TRACECLK, TRACESYNC, and 4-bit TRACEPKT. |
| Package | HVQFN48 (7 mm × 7 mm × 0.85 mm), thermal-enhanced, no-lead, 48-terminal package (SOT619-1). |
Pinout & Package
HVQFN48 package: plastic thermal-enhanced very thin quad flat package, no leads, 48 terminals, body size 7 mm × 7 mm × 0.85 mm (SOT619-1). Pin configuration identical across LPC2106FHN48, LPC2106FHN48/00, and LPC2106FHN48/01.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0.0/TXD0/PWM1 | UART 0 transmit / PWM output 1 | Primary serial output or PWM signal generation; 5 V tolerant, TTL-level I/O. |
| P0.1/RXD0/PWM3 | UART 0 receive / PWM output 3 | Serial data input or PWM channel; open-drain capable when used as I²C SDA/SCL. |
| P0.2/SCL/CAP0.0 | I²C clock / Timer 0 capture 0 | Open-drain 5 V tolerant I²C-bus clock line or edge-triggered timer input. |
| P0.3/SDA/MAT0.0 | I²C data / Timer 0 match 0 | Open-drain 5 V tolerant I²C-bus data line or configurable timer output. |
| P0.19/MAT1.2/TCK | Timer 1 match 2 / JTAG test clock | Primary JTAG TCK input (must be < CCLK/6); also serves as timer output or GPIO. |
| P0.27/TRACEPKT0/TRST | Trace packet bit 0 / JTAG test reset | Secondary JTAG TRST input and ETM trace data bit; internal pull-up enabled. |
| VDD(1V8) | Core power supply | 1.8 V ±8.3 % regulated supply for CPU and internal logic; decoupling required. |
| VDD(3V3) | I/O power supply | 3.3 V ±10 % supply for all GPIO and peripheral I/O; enables 5 V tolerant operation. |
| RESET | Active-low reset input | TTL-level, 5 V tolerant, hysteresis-enabled external reset; asserts on low pulse ≥100 ns. |
Key Features
| Feature | Design Value |
|---|---|
| Fast GPIO | Port pin toggle speed up to 3.5× faster than legacy LPC210x; real-time read access regardless of function mode. |
| Fractional Baud Rate Generators | UART 0/1 support precise non-integer baud rates (e.g., 115200, 921600) without external clock dividers. |
| Hardware Flow Control | Full RTS/CTS/DSR/DTR/DCD/RI modem handshaking implemented in UART 1 hardware - no CPU overhead. |
| SSP Serial Controller | Buffered SPI/SSI/Microwire interface with programmable data length and master-mode enhancements. |
| Diversified Code Read Protection | Multiple CRP levels (CRP1–CRP3) prevent unauthorized flash readout while allowing selective debug access. |
Applications
| Industrial Control Systems | Protocol Conversion Gateways |
|---|---|
Use Scenario: Real-time motor control and sensor monitoring in PLCs and CNC equipment with space-constrained enclosures. IC Role / Device Role / Timing Role: Main system controller executing deterministic control loops using PWM outputs, timer-captured encoder signals, and UART-based HMI communication. Use Value: 60 MHz ARM7TDMI-S core with 64 kB SRAM ensures sub-millisecond loop response; 5 V tolerant GPIO simplifies interfacing with legacy industrial sensors and actuators. | Use Scenario: Bridging Modbus RTU over RS-485 to MQTT over Wi-Fi/Ethernet in smart building infrastructure. IC Role / Device Role / Timing Role: Protocol translation engine managing dual UARTs (one for fieldbus, one for host interface), SPI-connected transceivers, and TCP/IP stack offload. Use Value: Dual UARTs with hardware flow control and fractional baud rate generators ensure reliable timing-critical serial framing; 128 kB flash hosts protocol stacks and firmware updates. |
| Low-End Imaging Devices | Voice Recognition Terminals |
Use Scenario: Compact document scanners and thermal printers requiring image buffering and real-time motor timing. IC Role / Device Role / Timing Role: Image acquisition controller synchronizing CMOS sensor readout (via GPIO/timers), buffering raw data in SRAM, and driving stepper motors via PWM. Use Value: 64 kB on-chip SRAM provides sufficient line buffer for VGA-resolution grayscale capture; fast GPIO enables precise pixel clock generation. | Use Scenario: Standalone voice command modules in home automation hubs with local keyword spotting. IC Role / Device Role / Timing Role: Audio preprocessor capturing analog input via external ADC, running lightweight DSP algorithms, and triggering actions via GPIO or UART. Use Value: 60 MHz CPU delivers sufficient MIPS for MFCC extraction and pattern matching; dual timers support precise audio sample timing and wake-on-voice latency control. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC2106FBD48/01 | LQFP48 package (7 mm × 7 mm × 1.4 mm); same electrical specs, flash, RAM, and peripherals. | Better suited for through-hole prototyping or manual rework; less thermal efficiency than HVQFN48. | Select when board assembly uses standard QFP reflow or requires mechanical robustness over thermal performance. |
| LPC2148FBD64 | 64-pin LQFP; adds USB 2.0 device controller, 512 kB flash, 96 kB SRAM, and 8-channel ADC - not pin-compatible. | Enables USB connectivity and higher-resolution analog sensing; larger footprint and higher power consumption. | Choose only when USB interface or expanded analog I/O is mandatory; requires PCB redesign and firmware adaptation. |
Compared with LPC2106FBD48/01, the LPC2106FHN48/01 offers superior thermal dissipation in space-constrained designs; compared with LPC2148FBD64, it trades USB/analog capability for smaller size, lower cost, and proven stability in legacy industrial deployments.
Availability
LPC2106FHN48/01 is available at Aetrix Electronics and suitable for industrial control systems, protocol conversion gateways, and low-end imaging devices requiring stable component supply, long-term lifecycle assurance, and qualified sourcing from NXP's discontinued-but-supported product portfolio.
Supply support for LPC2106FHN48/01 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader delivering secure, scalable solutions for automotive, industrial, IoT, and mobile applications.
The LPC2100 series was designed as a cost-optimized, high-integration 32-bit microcontroller family targeting space- and power-constrained embedded systems requiring rich serial connectivity and real-time responsiveness.
FAQ
What is the operating temperature range for the LPC2106FHN48/01?
The LPC2106FHN48/01 is rated for industrial operation from −40 °C to +85 °C. This range is confirmed in Table 2 of the official NXP datasheet and applies specifically to all /01-suffixed variants including LPC2106FHN48/01. The device maintains full specification compliance - including 60 MHz CPU operation, flash programming, and peripheral functionality - across this entire range.
Does the LPC2106FHN48/01 support in-system programming (ISP)?
Yes, the LPC2106FHN48/01 supports In-System Programming via its UART0 interface using the on-chip bootloader. Flash programming takes 1 ms per 512-byte line, and sector or full-chip erase completes in 400 ms. This capability is inherent to the LPC2106 part number and is fully functional in the LPC2106FHN48/01 variant, enabling field firmware updates without removing the device from the PCB.
How many UART interfaces does the LPC2106FHN48/01 include, and what advanced features do they offer?
The LPC2106FHN48/01 includes two UART interfaces (UART0 and UART1). Both support fractional baud rate generation, hardware auto-bauding, and full handshake flow control (RTS/CTS/DSR/DTR/DCD/RI) implemented entirely in hardware - eliminating CPU polling overhead. These features are explicitly documented for LPC2104/2105/2106/01 devices and apply directly to the LPC2106FHN48/01.
What debug and trace capabilities are integrated into the LPC2106FHN48/01?
The LPC2106FHN48/01 integrates EmbeddedICE-RT for real-time breakpoint and watchpoint debugging, plus an Embedded Trace Macrocell (ETM) supporting non-intrusive instruction trace. Trace signals include TRACECLK, TRACESYNC, and four TRACEPKT lines - all accessible on dedicated HVQFN48 pins (P0.22, P0.26, P0.27–P0.30). This trace capability is confirmed for LPC2106/01 devices and functions identically in the LPC2106FHN48/01 package.
Is the LPC2106FHN48/01 pin-compatible with other LPC2106 variants such as LPC2106FBD48/01?
No - the LPC2106FHN48/01 uses an HVQFN48 package (SOT619-1), while LPC2106FBD48/01 uses LQFP48 (SOT313-2). Although both have 48 terminals and identical pin functions, their physical layouts differ: HVQFN48 has perimeter pads with no leads, whereas LQFP48 has gull-wing leads. PCB layout, soldering profile, and thermal design must be adapted accordingly; they are not drop-in replacements.
LPC2106FHN48/01,55 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 48-VFQFN Exposed Pad
- Series:
- LPC2100
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- ARM7®
- Core Size:
- 16/32-Bit
- Speed:
- 60MHz
- Connectivity:
- I2C, Microwire, SPI, SSI, SSP, UART/USART
- Peripherals:
- POR, PWM, WDT
- Number of I/O:
- 32
- Program Memory Size:
- 128KB (128K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 64K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.65V ~ 3.6V
- Data Converters:
- -
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC2106FHN48/01,55 FAQ
1.How can I place an order for LPC2106FHN48/01,55 through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC2106FHN48/01,55 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC2106FHN48/01,55 reliable?
The price and inventory of LPC2106FHN48/01,55 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC2106FHN48/01,55 is usually 5 days.
3.What payment methods are accepted for LPC2106FHN48/01,55?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC2106FHN48/01,55 transactions.
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4.How is shipping managed for LPC2106FHN48/01,55?
LPC2106FHN48/01,55 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC2106FHN48/01,55 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC2106FHN48/01,55?
For technical support, including LPC2106FHN48/01,55 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC2106FHN48/01,55 requirements.
6.How does Aetrix verify that LPC2106FHN48/01,55 is sourced from the original manufacturer or authorized distributors?
All LPC2106FHN48/01,55 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC2106FHN48/01,55 meets industry standards.
7.What is the process for return or replacement of LPC2106FHN48/01,55?
All LPC2106FHN48/01,55 units undergo pre-shipment inspection (PSI). If there is an issue with LPC2106FHN48/01,55, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC2106FHN48/01,55 part is unused and in its original packaging.
Return procedure for LPC2106FHN48/01,55:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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