NXP Semiconductors LPC2119FBD64/01EL
- Part No.:
- LPC2119FBD64/01EL
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 64-LQFP
- Datasheet:
-
LPC2119FBD64/01EL.pdf
- Description:
- IC MCU 16/32B 128KB FLASH 64LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LPC2119FBD64/01EL from NXP Semiconductors is a 16/32-bit ARM7TDMI-S microcontroller in LQFP64 package, featuring 128 kB flash, 16 kB SRAM, dual CAN 2.0B interfaces, four-channel 10-bit ADC (2.44 µs conversion), and 46 GPIO pins with nine external interrupt inputs - deployed in automotive control units, industrial PLCs, medical monitoring systems, and CAN-based gateway devices.
For engineers reviewing the LPC2119FBD64/01EL datasheet, LPC2119FBD64/01EL pinout, LPC2119FBD64/01EL application, or LPC2119FBD64/01EL equivalent, this page delivers verified technical context, validated pin functions, real-world use cases, and two confirmed alternative parts for embedded system design and BOM optimization.
Technical Context
The LPC2119FBD64/01EL implements an ARM7TDMI-S core with Thumb instruction set support, enabling 32-bit performance at 60 MHz while reducing code size by >30% in 16-bit mode. Its memory subsystem includes a 128-bit wide flash interface with accelerator, delivering full-speed execution without wait states.
Peripheral integration centers on real-time determinism: dual CAN controllers with advanced acceptance filters, four 32-bit timers (eight capture/compare channels), six PWM outputs, and a dedicated 10-bit ADC with per-channel result registers - all accessible via Fast GPIO registers that enable port toggling up to 3.5× faster than legacy LPC2000 devices.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM7TDMI-S 16/32-bit RISC processor with Thumb mode and EmbeddedICE-RT debug support |
| Max Clock Speed | 60 MHz via on-chip PLL (100 µs settling time); enables deterministic real-time response in control loops |
| Flash Memory | 128 kB ISP/IAP flash with 100,000 erase/write cycles and 20-year data retention |
| SRAM | 16 kB on-chip SRAM accessible as 8/16/32-bit; supports fast interrupt service routines and stack operations |
| ADC | Four-channel 10-bit successive approximation ADC with 2.44 µs conversion time and dedicated result registers per channel |
| CAN Interfaces | Two independent CAN 2.0B controllers supporting up to 1 Mbit/s; each with programmable acceptance filters |
| I/O Capability | 46 total GPIO pins (5 V tolerant), including nine edge/level-sensitive external interrupt inputs and Fast GPIO register access |
| Power Supply | Dual-rail operation: 1.65–1.95 V (1.8 V ±0.15 V) core voltage and 3.0–3.6 V (3.3 V ±10 %) I/O voltage |
Pinout & Package
LQFP64 package (SOT314-2), 10 × 10 × 1.4 mm body, with exposed pad not electrically connected. Pin 1 marked by dot; pins numbered counterclockwise.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0[0]/TXD0/PWM1 | UART0 transmit / PWM output 1 | Primary serial debug interface or motor control signal generation; shared function requires Pin Connect Block configuration |
| P0[25]/RD1 | CAN1 receiver input | Differential CAN bus input for first controller; requires external transceiver and termination |
| P0[23]/RD2 & P0[24]/TD2 | CAN2 receiver/transmitter | Second CAN channel physical layer interface; available only on LPC2119/2129 variants |
| P0[27]–P0[30]/AIN0–AIN3 | Analog inputs for ADC | Four dedicated 0–3 V analog inputs with direct connection to ADC; 5 V tolerant when configured as digital I/O |
| VDD(1V8), VDDA(1V8) | Core and analog 1.8 V supplies | Separate power domains minimize noise coupling into sensitive analog and PLL circuits |
| VDD(3V3), VDDA(3V3) | I/O and analog 3.3 V supplies | Independent 3.3 V rail for digital I/O and ADC reference; 5 V tolerant pads simplify level translation |
| RESET | Active-low reset input | TTL-compatible with hysteresis; low assertion during power-up forces bootloader entry if P0[14] is held low |
| P1[26]/RTCK | Returned test clock | JTAG synchronization signal enabling reliable debugging across variable CPU clock frequencies |
Key Features
| Feature | Design Value |
|---|---|
| Fast GPIO Registers | Relocated to ARM local bus for 3.5× faster port toggling vs. legacy LPC2000; enables precise timing-critical bit-banging (e.g., custom protocols) |
| Dedicated ADC Result Registers | One register per channel reduces interrupt latency and eliminates software polling overhead in high-throughput sampling |
| Fractional Baud Rate Generator | Enables exact UART0/1 baud rates (e.g., 115200 bps) across wide clock ranges without external crystal trimming |
| Embedded Trace Macrocell (ETM) | Non-intrusive real-time instruction trace without halting CPU; critical for validating timing behavior in safety-critical firmware |
| Code Read Protection (CRP) | Three security levels disable JTAG/ISP access to flash and RAM while permitting field firmware updates via ISP erase commands |
| Vectored Interrupt Controller (VIC) | 16 configurable IRQ priority slots plus FIQ support; enables sub-1 µs worst-case interrupt latency for time-critical events |
Applications
| Automotive Body Control Module | Industrial CAN Gateway |
|---|---|
Use Scenario: Centralized control of door locks, lighting, and window actuators using CAN communication with distributed ECUs. IC Role / Device Role / Timing Role: Main application MCU executing real-time control logic, managing dual CAN buses for inter-ECU messaging, and sampling analog sensor inputs (e.g., temperature, voltage). Use Value: Dual CAN controllers eliminate need for external bridge ICs; 128 kB flash accommodates multi-feature firmware with OTA update capability. |
Use Scenario: Protocol translation between CAN FD and RS-485 fieldbus in factory automation networks. IC Role / Device Role / Timing Role: Bridge processor handling message filtering, reformatting, and timestamping between heterogeneous industrial networks. Use Value: Fast GPIO and hardware UART flow control enable deterministic packet forwarding; 46 GPIO pins support status LEDs and hardware handshaking signals. |
| Medical Patient Monitor Interface | Energy Meter Data Logger |
Use Scenario: Acquisition and preprocessing of ECG, SpO₂, and respiration signals before transmission to host system. IC Role / Device Role / Timing Role: Signal acquisition MCU with synchronized 10-bit ADC sampling, real-time filtering, and CAN-based telemetry output. Use Value: Dedicated ADC result registers and 2.44 µs conversion time ensure minimal jitter in waveform reconstruction; CRP secures patient data firmware. |
Use Scenario: Tamper-resistant electricity meter collecting voltage/current samples and logging kWh data over 10+ years. IC Role / Device Role / Timing Role: Primary metering controller performing RMS calculations, RTC-based billing intervals, and secure flash storage of consumption history. Use Value: 100,000-flash endurance and 20-year data retention meet IEC 62053-21 requirements; dual CAN supports utility-side diagnostics and firmware updates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC2129FBD64/01 | 256 kB flash, same 16 kB SRAM, identical peripherals and pinout | Supports larger firmware images (e.g., integrated TCP/IP stack + CANopen stack) | Select when future firmware expansion or dual-application partitioning is required |
| LPC2368FBD100 | 100-pin LQFP, 512 kB flash, 96 kB SRAM, USB 2.0 device, Ethernet MAC, no CAN | Replaces CAN with USB/Ethernet connectivity; higher memory and peripheral count | Choose for network-connected devices requiring web-based configuration or remote firmware updates |
Compared with LPC2119FBD64/01EL, LPC2129FBD64/01 offers double flash capacity without layout changes, while LPC2368FBD100 shifts focus from CAN-centric control to networked data aggregation - making the former ideal for CAN-based field upgrades and the latter for cloud-connected edge nodes.
Availability
LPC2119FBD64/01EL is available at Aetrix Electronics and suitable for automotive control units, industrial gateways, and medical monitoring systems requiring stable component supply and long-term lifecycle assurance.
Supply support for LPC2119FBD64/01EL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications.
The LPC2100 series was designed for cost-sensitive, real-time embedded control in harsh environments - emphasizing CAN robustness, low-power operation, and debug visibility via ETM and EmbeddedICE-RT.
FAQ
What is the maximum operating frequency of the LPC2119FBD64/01EL?
The LPC2119FBD64/01EL achieves a maximum CPU clock of 60 MHz using its on-chip PLL with 100 µs settling time. This frequency is sustained across the full industrial temperature range (−40 °C to +85 °C) when supplied with 1.8 V core voltage and proper decoupling. The 128-bit wide flash interface ensures zero-wait-state execution at this speed.
Does the LPC2119FBD64/01EL support both CAN 2.0A and CAN 2.0B protocols?
Yes, the LPC2119FBD64/01EL's dual CAN controllers fully comply with ISO 11898-1:2003, supporting both standard (11-bit ID) and extended (29-bit ID) frames - i.e., CAN 2.0B. Each controller includes acceptance filtering logic and supports bit rates up to 1 Mbit/s, with programmable timing quanta for precise synchronization.
How many analog input channels does the LPC2119FBD64/01EL ADC support?
The LPC2119FBD64/01EL integrates a single 10-bit successive approximation ADC with four multiplexed analog input channels (AIN0–AIN3), each mapped to dedicated pins P0[27]–P0[30]. All channels operate over a 0–3 V measurement range and support burst conversion mode with optional trigger sources.
Is the LPC2119FBD64/01EL pin-compatible with the LPC2109FBD64/01?
No - while both share the LQFP64 package and identical pinout, the LPC2119FBD64/01EL includes additional functionality not present in the LPC2109FBD64/01: dual CAN (vs. single), 128 kB flash (vs. 64 kB), 16 kB SRAM (vs. 8 kB), and Fast GPIO registers. Hardware compatibility exists, but firmware must account for feature differences.
What debug interfaces are available on the LPC2119FBD64/01EL?
The LPC2119FBD64/01EL provides JTAG (TRST, TMS, TCK, TDI, TDO, RTCK) and EmbeddedICE-RT interfaces for real-time breakpoint and watchpoint debugging. It also supports non-intrusive instruction tracing via the Embedded Trace Macrocell (ETM), accessible through the trace port (P1[16–20], P1[21–24]).
LPC2119FBD64/01EL Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 64-LQFP
- Series:
- LPC2100
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM7®
- Core Size:
- 16/32-Bit
- Speed:
- 60MHz
- Connectivity:
- CANbus, I2C, Microwire, SPI, SSI, SSP, UART/USART
- Peripherals:
- POR, PWM, WDT
- Number of I/O:
- 46
- Program Memory Size:
- 128KB (128K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 16K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.65V ~ 3.6V
- Data Converters:
- A/D 4x10b SAR
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC2119FBD64/01EL FAQ
1.How can I place an order for LPC2119FBD64/01EL through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC2119FBD64/01EL on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC2119FBD64/01EL reliable?
The price and inventory of LPC2119FBD64/01EL are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC2119FBD64/01EL is usually 5 days.
3.What payment methods are accepted for LPC2119FBD64/01EL?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC2119FBD64/01EL transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC2119FBD64/01EL?
LPC2119FBD64/01EL orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC2119FBD64/01EL order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC2119FBD64/01EL?
For technical support, including LPC2119FBD64/01EL datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC2119FBD64/01EL requirements.
6.How does Aetrix verify that LPC2119FBD64/01EL is sourced from the original manufacturer or authorized distributors?
All LPC2119FBD64/01EL products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC2119FBD64/01EL meets industry standards.
7.What is the process for return or replacement of LPC2119FBD64/01EL?
All LPC2119FBD64/01EL units undergo pre-shipment inspection (PSI). If there is an issue with LPC2119FBD64/01EL, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC2119FBD64/01EL part is unused and in its original packaging.
Return procedure for LPC2119FBD64/01EL:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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