NXP Semiconductors LPC2119FBD64,151
- Part No.:
- LPC2119FBD64,151
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 64-LQFP
- Datasheet:
-
LPC2119FBD64,151.pdf
- Description:
- IC MCU 16/32B 128KB FLASH 64LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,843
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC2119FBD64,151 from NXP Semiconductors is a 16/32-bit ARM7TDMI-S microcontroller in LQFP64 package, featuring 128 kB flash, 16 kB SRAM, dual CAN 2.0B interfaces, four-channel 10-bit ADC (2.44 µs conversion), and 46 GPIO pins with nine external interrupt inputs - deployed in automotive control units and industrial CAN gateways.
For engineers reviewing the LPC2119FBD64,151 datasheet, LPC2119FBD64,151 pinout, LPC2119FBD64,151 application, or LPC2119FBD64,151 equivalent, key selection criteria include dual-CAN timing synchronization, 60 MHz CPU clock with PLL settling in 100 µs, 5 V-tolerant ADC input pads, Fast GPIO toggle performance, and CRP-enabled firmware security for embedded field updates.
Technical Context
The LPC2119FBD64,151 implements an ARM7TDMI-S core with Thumb instruction set support, enabling 32-bit execution at 60 MHz via a 128-bit wide memory interface and accelerator architecture. Its Vectored Interrupt Controller supports 16 prioritized IRQ channels plus FIQ, with dedicated registers for ADC results to minimize interrupt latency.
It integrates two independent CAN 2.0B controllers with advanced acceptance filters, buffered SSP supporting SPI/SSI/Microwire, and dual UARTs with fractional baud rate generators and hardware flow control - all mapped through a configurable Pin Connect Block to shared LQFP64 pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM7TDMI-S 16/32-bit RISC processor with Thumb mode for 30% smaller code size and minimal performance penalty. |
| Max Clock Speed | 60 MHz via on-chip PLL with 100 µs settling time - enables deterministic real-time response in CAN bus arbitration and PWM generation. |
| Memory | 128 kB on-chip flash (100k erase/write cycles, 20-year retention) and 16 kB SRAM - sufficient for dual-CAN protocol stacks and real-time control firmware. |
| ADC | Four-channel 10-bit successive approximation ADC with 2.44 µs conversion time and dedicated result registers - supports high-speed sensor sampling without CPU polling overhead. |
| CAN Interfaces | Two independent CAN 2.0B controllers supporting up to 1 Mbit/s data rate - enables redundant bus communication or gateway bridging between separate CAN networks. |
| I/O & Power | 46 GPIO pins (5 V tolerant when configured as digital I/O), dual power domains: 1.8 V ±0.15 V core and 3.3 V ±10% I/O - ensures robust operation in mixed-voltage automotive environments. |
| Debug & Security | EmbeddedICE-RT and ETM trace support, plus Diversified Code Read Protection (CRP) - allows secure in-field firmware updates and non-intrusive real-time instruction tracing. |
Pinout & Package
LPC2119FBD64,151 uses a plastic low-profile quad flat package (LQFP64), 10 × 10 × 1.4 mm (SOT314-2), with 64 leads and exposed thermal pad. Pin functions are multiplexed via the Pin Connect Block; all GPIO, peripheral, debug, and power pins are validated per NXP Rev. 7 datasheet.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0[0]/TXD0/PWM1 | UART0 transmit / PWM output | Primary serial debug interface or motor control signal; shares pin with PWM1 for compact motor driver designs. |
| P0[25]/RD1 & P0[23]/RD2 | CAN1/CAN2 receiver inputs | Differential receive paths for dual isolated CAN buses - requires external transceivers and termination. |
| P0[24]/TD2 & TD1 | CAN2/CAN1 transmitter outputs | Open-drain outputs driving external CAN transceivers; supports simultaneous dual-bus transmission. |
| P0[27–30]/AIN0–AIN3 | Analog inputs | Four dedicated 0–3 V analog inputs with 5 V tolerance in digital mode - enables direct connection to legacy sensors without level-shifting. |
| P1[16–19]/TRACEPKT0–3 & P1[20]/TRACESYNC | ETM trace interface | Eight-pin parallel trace port supporting non-intrusive real-time instruction execution monitoring - requires compatible debugger and trace pod. |
| VDD(1V8), VDDA(1V8) | Core/analog power | Separate 1.8 V supplies for digital core and analog circuitry - mandatory isolation minimizes noise coupling into ADC and PLL. |
| RESET | Active-low reset input | TTL-compatible with hysteresis and 5 V tolerance - enables direct connection to system-level reset supervisors. |
Key Features
| Feature | Design Value |
|---|---|
| Fast GPIO Registers | Port pin toggling up to 3.5× faster than legacy LPC2000 devices - critical for bit-banged protocols and real-time I/O response. |
| Dedicated ADC Result Registers | One register per channel reduces interrupt service overhead and eliminates read-modify-write latency during burst conversions. |
| Fractional Baud Rate Generators | UART0/1 support precise baud rates across wide clock ranges - eliminates timing errors in multi-drop RS-485 or modem-linked systems. |
| SSP Serial Controller | Hardware-buffered SPI/SSI/Microwire interface with programmable data length - simplifies interfacing with displays, EEPROMs, and digital potentiometers. |
| CRP Security Levels | Three-tier Code Read Protection disables JTAG/ISP access while preserving full flash erase capability - enables secure boot and OTA update deployment. |
| External Event Counting | General-purpose timers operate as external event counters - supports RPM measurement, pulse-width analysis, and encoder position tracking. |
Applications
| Automotive Body Control Module | Industrial CAN Gateway |
|---|---|
Use Scenario: Centralized control of door locks, lighting, and window actuators using CAN bus commands from dashboard ECU. IC Role / Device Role / Timing Role: Primary MCU executing real-time CAN message filtering, PWM dimming control, and fault-safe GPIO management. Use Value: Dual CAN controllers enable concurrent communication on chassis and comfort networks; 46 GPIOs drive relays and monitor switches without external expanders. |
Use Scenario: Protocol translation between CANopen and Modbus RTU networks in factory automation PLCs. IC Role / Device Role / Timing Role: Bridge controller managing time-synchronized message forwarding, buffer management, and error recovery across heterogeneous buses. Use Value: 60 MHz ARM7TDMI-S core executes dual-stack protocol handling with <100 µs inter-frame latency; 128 kB flash stores both protocol stacks and configuration tables. |
| Medical Infusion Pump Controller | Fault-Tolerant Maintenance Bus Node |
Use Scenario: Closed-loop motor control and pressure sensing in battery-powered portable infusion devices requiring IEC 62304 compliance. IC Role / Device Role / Timing Role: Safety-critical real-time controller performing ADC-based pressure feedback, stepper motor sequencing, and watchdog-monitored operation. Use Value: Four-channel 10-bit ADC samples pressure transducers at >400 kSPS; CRP prevents unauthorized firmware modification; RTC supports dose logging with timestamps. |
Use Scenario: Redundant diagnostic node monitoring power supply voltages, temperature, and fan status across multiple rack-mounted telecom equipment shelves. IC Role / Device Role / Timing Role: Standalone maintenance agent collecting sensor data, generating alerts, and reporting via CAN bus to central supervisor. Use Value: Nine external interrupt pins handle asynchronous fault signals from diverse subsystems; low-power Idle/Power-down modes extend battery backup runtime. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC2129FBD64,151 | 256 kB flash, same 16 kB SRAM, identical dual-CAN and peripheral set - no pinout or clock difference. | Suitable where larger firmware image size is required (e.g., integrated bootloader + application + crypto stack). | Select when firmware exceeds 128 kB or future-proofing for feature expansion is needed; same PCB layout and drivers. |
| LPC2214FBD144,15 | 144-pin LQFP, 256 kB flash, 64 kB SRAM, enhanced peripherals including USB 2.0 device, but no CRP level 3 and higher power consumption. | Better suited for complex HMI or USB-connected diagnostics tools - not drop-in due to package and pin count mismatch. | Choose only if USB connectivity or larger RAM is mandatory; requires new PCB layout and driver adaptation. |
Compared with LPC2119FBD64,151, the LPC2129FBD64,151 offers scalable flash capacity without design change, while the LPC2214FBD144,15 introduces USB and larger memory at the cost of footprint, power, and compatibility - making LPC2119FBD64,151 optimal for cost-sensitive dual-CAN edge nodes.
Availability
LPC2119FBD64,151 is available at Aetrix Electronics and suitable for automotive body control modules, industrial CAN gateways, and medical infusion pump controllers requiring stable component supply throughout extended production lifecycles.
Supply support for LPC2119FBD64,151 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in ARM-based microcontrollers and real-time embedded systems.
The LPC2100 series was designed for cost-optimized, low-power 32-bit control in resource-constrained environments - targeting automotive sub-systems, industrial networking, and safety-critical medical devices requiring dual-CAN and deterministic real-time response.
FAQ
What is the maximum operating frequency of the LPC2119FBD64,151?
The LPC2119FBD64,151 achieves a maximum CPU clock frequency of 60 MHz using its on-chip Phase-Locked Loop (PLL), which settles in 100 µs. This frequency is sustained by the 128-bit wide memory interface and accelerator architecture, enabling full-speed 32-bit instruction execution without wait states - essential for time-critical CAN message processing and PWM generation in the LPC2119FBD64,151.
Does the LPC2119FBD64,151 support dual CAN interfaces?
Yes, the LPC2119FBD64,151 integrates two independent CAN 2.0B controllers supporting data rates up to 1 Mbit/s each, with advanced acceptance filters for message filtering. This dual-CAN capability is confirmed in Table 2 of the datasheet and distinguishes it from the single-CAN LPC2109FBD64,151 - making the LPC2119FBD64,151 suitable for gateway or redundancy applications requiring simultaneous bus access.
What are the power supply requirements for the LPC2119FBD64,151?
The LPC2119FBD64,151 requires two separate power domains: a 1.8 V ±0.15 V supply (VDD(1V8) and VDDA(1V8)) for the core and analog circuitry, and a 3.3 V ±10% supply (VDD(3V3) and VDDA(3V3)) for I/O and ADC reference. The analog grounds (VSSA, VSSA(PLL)) must be isolated from digital ground to maintain ADC accuracy and PLL stability in the LPC2119FBD64,151.
Can the LPC2119FBD64,151 perform in-system programming (ISP)?
Yes, the LPC2119FBD64,151 supports In-System Programming via its UART0 interface using the on-chip bootloader. Flash programming takes 1 ms per 512-byte line, and sector or full-chip erase completes in 400 ms. This ISP capability enables field firmware updates without removing the LPC2119FBD64,151 from the target board - critical for remote maintenance and security patching.
Is the LPC2119FBD64,151 pin-compatible with other LPC21xx devices?
The LPC2119FBD64,151 shares the same LQFP64 package (SOT314-2) and identical pin configuration with LPC2109FBD64,151 and LPC2129FBD64,151, including matching power, reset, oscillator, and peripheral pin assignments. However, functional differences exist - such as flash size, SRAM, and CAN channel count - so firmware and power design must be verified per device; the LPC2119FBD64,151 is mechanically and electrically pin-compatible but not functionally identical.
LPC2119FBD64,151 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 64-LQFP
- Series:
- LPC2100
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- ARM7®
- Core Size:
- 16/32-Bit
- Speed:
- 60MHz
- Connectivity:
- CANbus, I2C, Microwire, SPI, SSI, SSP, UART/USART
- Peripherals:
- POR, PWM, WDT
- Number of I/O:
- 46
- Program Memory Size:
- 128KB (128K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 16K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.65V ~ 3.6V
- Data Converters:
- A/D 4x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC2119FBD64,151 FAQ
1.How can I place an order for LPC2119FBD64,151 through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC2119FBD64,151 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC2119FBD64,151 reliable?
The price and inventory of LPC2119FBD64,151 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC2119FBD64,151 is usually 5 days.
3.What payment methods are accepted for LPC2119FBD64,151?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC2119FBD64,151 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC2119FBD64,151?
LPC2119FBD64,151 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC2119FBD64,151 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC2119FBD64,151?
For technical support, including LPC2119FBD64,151 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC2119FBD64,151 requirements.
6.How does Aetrix verify that LPC2119FBD64,151 is sourced from the original manufacturer or authorized distributors?
All LPC2119FBD64,151 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC2119FBD64,151 meets industry standards.
7.What is the process for return or replacement of LPC2119FBD64,151?
All LPC2119FBD64,151 units undergo pre-shipment inspection (PSI). If there is an issue with LPC2119FBD64,151, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC2119FBD64,151 part is unused and in its original packaging.
Return procedure for LPC2119FBD64,151:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC2119FBD64,151 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

