NXP Semiconductors LPC2220FET144/G,51
- Part No.:
- LPC2220FET144/G,51
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 144-TFBGA
- Datasheet:
-
LPC2220FET144/G,51.pdf
- Description:
- IC MCU 16/32BIT ROMLESS 144TFBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LPC2220FET144/G from NXP Semiconductors is a 32-bit ARM7TDMI-S microcontroller in TFBGA144 package, featuring 64 kB on-chip SRAM, 75 MHz CPU clock via programmable PLL, eight-channel 10-bit ADC (2.44 µs conversion), dual 32-bit timers with PWM and capture, and dual UARTs with fractional baud rate generation - deployed in industrial control and medical systems requiring deterministic real-time I/O.
For engineers reviewing the LPC2220FET144/G datasheet, LPC2220FET144/G pinout, LPC2220FET144/G application, or LPC2220FET144/G equivalent, key selection criteria include 5 V-tolerant GPIO count (up to 76 pins), external memory interface (4 banks, up to 16 MB each), Fast GPIO capability, and integrated trace/debug support for embedded firmware development.
Technical Context
The LPC2220FET144/G implements ARM7TDMI-S core with Thumb instruction set for 30 % code size reduction versus ARM mode, while maintaining near-native performance. Its memory subsystem includes configurable external bus interface supporting 8/16/32-bit data width across four independent banks.
Real-time peripherals include two 32-bit timers (each with four capture/compare channels), RTC, watchdog, and an 8-channel 10-bit ADC with dedicated result registers to minimize interrupt latency. Serial connectivity comprises two UARTs (16C550-compatible), Fast I²C (400 kbit/s), two SPIs, and one SSP - all accessible via multiplexed GPIO pins managed by Pin Connect Block.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM7TDMI-S 32-bit RISC processor with Thumb mode support for compact firmware deployment |
| Max Clock Speed | 75 MHz via on-chip PLL (100 µs settling time), enabling deterministic real-time response |
| On-chip RAM | 64 kB static RAM - sufficient for bootloader, RTOS kernel, and application buffers without external memory |
| ADC | 8-channel 10-bit SAR ADC with 2.44 µs conversion time and dedicated result registers to reduce ISR overhead |
| I/O Voltage | 5 V tolerant I/O pads (3.0–3.6 V I/O supply) - simplifies interfacing with legacy 5 V logic and sensors |
| External Memory Interface | Configurable 4-bank controller supporting 8/16/32-bit data width, up to 16 MB per bank - enables NOR flash, SRAM, or peripheral expansion |
| Debug Interface | EmbeddedICE-RT and Embedded Trace modules with JTAG (TRST/TCK/TMS/TDI/TDO) and trace port (TRACEPKT0–3, TRACESYNC, TRACECLK) |
Pinout & Package
Package: TFBGA144 (SOT569-2), plastic thin fine-pitch ball grid array, 12 × 12 × 0.8 mm body, 144 solder balls.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1 (P2.22/D22) | External memory data line 22 | Part of 32-bit parallel data bus for BANK0–BANK3; supports high-speed memory read/write cycles |
| A3 (P1.28/TDI) | JTAG Test Data Input | Serial input for boundary-scan and debug programming; requires synchronous TCK edge |
| B1 (VDD(3V3)) | I/O power supply | 3.3 V ±10 % supply for all digital I/O ports; decoupling required per datasheet layout guidelines |
| C5 (RESET) | Active-low reset input | TTL-compatible, 5 V tolerant; asserts internal reset state and forces boot sequence initialization |
| D13 (P0.17) | Capture input / SPI1 clock / Timer1 match | Multi-function pin configurable via Pin Connect Block; used for precise event timing or synchronous serial communication |
| G3 (P2.30/D30/AIN4) | Analog input 4 / memory data line 30 | Shared analog/digital function - ADC channel active only when digital section is disabled per configuration |
| K6 (P0.1/RXD0/PWM3/EINT0) | UART0 receive / PWM output / external interrupt | Hardware-multiplexed pin enabling simultaneous serial comms, motor control signaling, and interrupt-driven event detection |
| N1 (VDD(1V8)) | Core power supply | 1.65–1.95 V supply for ARM7TDMI-S core and internal logic; must be isolated from I/O rail to prevent noise coupling |
Key Features
| Feature | Design Value |
|---|---|
| Fast GPIO ports | Port pin toggle speed up to 3.5× faster than standard GPIO - critical for bit-banged protocols and real-time waveform generation |
| Dedicated ADC result registers | Eliminates need for software register reads during interrupt service, reducing latency and jitter in time-critical sampling |
| Fractional baud rate generator | Enables exact UART bit rates (e.g., 115.2 kbps at 75 MHz CCLK) without external crystal tuning or clock dividers |
| Configurable external memory interface | Supports mixed-width peripherals (e.g., 16-bit NOR flash + 8-bit I/O expanders) across four independent address banks |
| 5 V tolerant I/O with glitch filtering | Digital inputs reject sub-3 ns noise pulses - improves reliability in electrically noisy industrial environments |
| Embedded Trace Interface | Real-time instruction trace via dedicated trace port pins - enables non-intrusive profiling and timing analysis in production firmware |
Applications
| Industrial PLC I/O Module | Medical Patient Monitor Front-End |
|---|---|
Use Scenario: Real-time acquisition of analog sensor signals (ECG, SpO₂) and digital status inputs from multiple patient beds. IC Role / Device Role / Timing Role: Central MCU managing 8-channel ADC sampling, UART-based telemetry to central station, and GPIO-controlled alarm outputs. Use Value: Dedicated ADC result registers and 2.44 µs conversion enable synchronized multi-channel sampling at ≥1 kHz without CPU bottleneck. |
Use Scenario: Compact, low-power bedside monitor integrating analog front-end, display interface, and wireless upload via UART-to-BLE bridge. IC Role / Device Role / Timing Role: Main controller executing real-time signal processing, driving segmented LCD via GPIO, and managing UART flow control with hardware handshaking. Use Value: Fractional baud rate generator ensures precise 115200 bps UART link to BLE module despite 75 MHz system clock - eliminating timing errors in data transmission. |
| Access Control Panel | Protocol Gateway for Building Automation |
Use Scenario: Secure door entry system reading RFID tags, validating credentials, and actuating magnetic locks with tamper detection. IC Role / Device Role / Timing Role: Host processor running secure authentication stack, managing contactless reader interface (SPI), and monitoring 5 V-tolerant door sensor inputs. Use Value: 5 V tolerant GPIOs directly interface legacy 5 V Wiegand readers and lock drivers - no level-shifter components required. |
Use Scenario: Field gateway translating Modbus RTU (RS-485) to BACnet/IP over Ethernet, bridging HVAC controllers and building management systems. IC Role / Device Role / Timing Role: Dual-protocol bridge MCU handling UART-based Modbus framing, TCP/IP stack offload (via external PHY), and real-time timer-based polling intervals. Use Value: Two independent 32-bit timers with four capture/compare channels allow precise 100 ms Modbus response window enforcement and watchdog-triggered fail-safe transitions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC2210FBD144 | 16 kB SRAM, LQFP144 package, no Fast GPIO or SSP | Lower memory and peripheral feature set; suitable for cost-sensitive, non-real-time control | Select when design does not require >32 kB RAM or sub-µs ADC latency |
| LPC2220FBD144 | Identical core specs but LQFP144 package instead of TFBGA144 | Same functionality with through-hole/reflow-compatible footprint; easier prototyping and rework | Choose for manual assembly, test fixtures, or designs avoiding fine-pitch BGA routing |
Compared with LPC2210FBD144, the LPC2220FET144/G provides 4× more SRAM and enhanced peripherals for deterministic real-time tasks; versus LPC2220FBD144, it offers higher board density and thermal performance in space-constrained industrial enclosures.
Availability
LPC2220FET144/G is available at Aetrix Electronics and suitable for industrial control, medical instrumentation, and access control systems requiring stable component supply, long-term lifecycle support, and qualified automotive-grade sourcing.
Supply support for LPC2220FET144/G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company specializing in secure connectivity solutions for automotive, industrial, and IoT applications.
The LPC22xx series was designed for cost-effective, real-time embedded control in resource-constrained environments - emphasizing low-power operation, robust I/O tolerance, and integrated debug infrastructure for rapid firmware development.
FAQ
What is the maximum operating frequency of the LPC2220FET144/G?
The LPC2220FET144/G achieves a maximum CPU clock of 75 MHz using its on-chip Phase-Locked Loop (PLL). This frequency is programmable with a 100 µs settling time and supported across the full industrial temperature range (−40 °C to +85 °C). The LPC2220FET144/G maintains this performance while delivering deterministic interrupt response and real-time peripheral timing.
Does the LPC2220FET144/G include on-chip flash memory?
No, the LPC2220FET144/G is a flashless microcontroller. It contains 64 kB of on-chip static RAM but no internal flash memory. Firmware must be loaded externally via the serial bootloader (using UART0) or executed from external memory mapped into the 4-bank external memory interface. This architecture allows flexible code storage options including NOR flash or EEPROM.
How many analog inputs does the LPC2220FET144/G support?
The LPC2220FET144/G integrates an 8-channel 10-bit successive approximation ADC. Analog inputs AIN0 through AIN7 are assigned to specific GPIO pins (e.g., P0.27, P0.28, P2.30, P2.31, P3.28, P3.29), all 5 V tolerant when configured for analog use. Each channel supports conversion times as low as 2.44 µs, and dedicated result registers reduce interrupt servicing overhead.
Is the LPC2220FET144/G pin-compatible with the LPC2210 series?
The LPC2220FET144/G shares identical pin functions and ball allocation with the LPC2210/01 family in TFBGA144 packaging, but differs in memory size (64 kB vs. 16 kB) and enabled features (Fast GPIO, SSP, enhanced UARTs). While electrical and mechanical pinout matches, firmware and PCB layout must account for functional differences - especially ADC result register usage and memory map configuration.
What debug interfaces are supported by the LPC2220FET144/G?
The LPC2220FET144/G supports JTAG (TRST/TCK/TMS/TDI/TDO) via dedicated pins and includes EmbeddedICE-RT for real-time debugging. It also provides full Embedded Trace Interface with dedicated trace port pins (TRACEPKT0–3, TRACESYNC, TRACECLK, TRACECLK) for non-intrusive instruction-level tracing - essential for optimizing timing-critical firmware and diagnosing race conditions in the LPC2220FET144/G.
LPC2220FET144/G,51 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 144-TFBGA
- Series:
- LPC2200
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- ARM7®
- Core Size:
- 16/32-Bit
- Speed:
- 75MHz
- Connectivity:
- EBI/EMI, I2C, Microwire, SPI, SSI, SSP, UART/USART
- Peripherals:
- POR, PWM, WDT
- Number of I/O:
- 76
- Program Memory Size:
- -
- Program Memory Type:
- ROMless
- EEPROM Size:
- -
- RAM Size:
- 64K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.65V ~ 3.6V
- Data Converters:
- A/D 8x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC2220FET144/G,51 FAQ
1.How can I place an order for LPC2220FET144/G,51 through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC2220FET144/G,51 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC2220FET144/G,51 reliable?
The price and inventory of LPC2220FET144/G,51 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC2220FET144/G,51 is usually 5 days.
3.What payment methods are accepted for LPC2220FET144/G,51?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC2220FET144/G,51 transactions.
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4.How is shipping managed for LPC2220FET144/G,51?
LPC2220FET144/G,51 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC2220FET144/G,51 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC2220FET144/G,51?
For technical support, including LPC2220FET144/G,51 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC2220FET144/G,51 requirements.
6.How does Aetrix verify that LPC2220FET144/G,51 is sourced from the original manufacturer or authorized distributors?
All LPC2220FET144/G,51 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC2220FET144/G,51 meets industry standards.
7.What is the process for return or replacement of LPC2220FET144/G,51?
All LPC2220FET144/G,51 units undergo pre-shipment inspection (PSI). If there is an issue with LPC2220FET144/G,51, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC2220FET144/G,51 part is unused and in its original packaging.
Return procedure for LPC2220FET144/G,51:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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