NXP Semiconductors LPC2361FBD100,551

Overview

LPC2361FBD100 from NXP Semiconductors is a 32-bit ARM7TDMI-S microcontroller operating at up to 72 MHz, featuring 64 kB flash, 8 kB local bus SRAM, 16 kB Ethernet buffer SRAM (usable as general-purpose), 8 kB USB/general-purpose DMA SRAM, and 2 kB battery-backed RTC SRAM. It integrates four UARTs, two CAN channels, USB 2.0 device/OTG, SPI/SSP/I²C/I²S interfaces, 10-bit ADC/DAC, PWM, and 70 GPIO pins - deployed in industrial control gateways requiring deterministic serial protocol bridging.

For engineers reviewing the LPC2361FBD100 datasheet, LPC2361FBD100 pinout, LPC2361FBD100 application, or LPC2361FBD100 equivalent, key selection criteria include its dual-AHB architecture supporting concurrent USB and DMA transfers, absence of integrated Ethernet MAC (distinguishing it from LPC2362), 100-pin LQFP package with 5 V-tolerant I/O, and support for real-time interrupt handling via Advanced Vectored Interrupt Controller (VIC).

Technical Context

The LPC2361FBD100 implements an ARM7TDMI-S core with Thumb/ARM instruction set support, enabling 32-bit code execution at full 72 MHz via a 128-bit wide memory interface and accelerator architecture. Its dual AHB subsystem separates CPU access to flash/SRAM from peripheral DMA traffic, eliminating bus contention between USB, GPDMA, and instruction fetch.

Peripheral integration follows a modular, pin-multiplexed architecture: all serial interfaces (UARTs, CAN, SSP, I²C, I²S, USB) share dedicated AHB slaves, while timers, ADC/DAC, and PWM operate on APB. The 70 GPIO lines are distributed across five ports (P0–P4), with up to 12 pins configurable as edge- or level-sensitive external interrupts - including EINT0–EINT3 on PORT2.

Key Specifications

Pinout & Package

LPC2361FBD100 uses a 100-lead LQFP package (SOT407-1), 14 mm × 14 mm × 1.4 mm body, with 5 V-tolerant I/O pins (TTL levels + hysteresis) and dedicated analog power domains (VDDA, VSSA, VREF).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microcontroller applications.

Compared with LPC2361FBD100, the LPC2362FBD100 adds Ethernet MAC but requires dedicated PORT1 pins and RMII PHY, while LPC2364FBD100 extends USB capability to host mode without altering memory map or GPIO count - both retain identical 100-pin LQFP packaging and core timing behavior.

Availability

LPC2361FBD100 is available at Aetrix Electronics and suitable for industrial control gateways, medical data acquisition systems, and embedded communications backhaul nodes requiring stable component supply and long-term lifecycle assurance.

Supply support for LPC2361FBD100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in ARM-based microcontrollers and mixed-signal integration.

The LPC2300 series targets high-integration, cost-sensitive embedded systems requiring rich serial connectivity and deterministic real-time performance - designed specifically for protocol conversion, gateway, and control applications without Ethernet PHY dependency.

FAQ

Does LPC2361FBD100 include an Ethernet MAC?

No, LPC2361FBD100 does not integrate an Ethernet MAC. That feature is exclusive to the LPC2362FBD100 variant. The LPC2361FBD100 shares the same 100-pin LQFP package and core peripheral set but omits the Ethernet MAC, ENET_TXD0/ENET_RXD0 pins, and associated AHB Ethernet slave - confirmed in Table 2 of the official datasheet.

What is the maximum operating frequency of LPC2361FBD100?

The LPC2361FBD100 operates at a maximum CPU clock frequency of 72 MHz, achieved via its on-chip PLL driven by either the external crystal (1–25 MHz) or the internal 4 MHz RC oscillator. This 72 MHz rate applies to ARM and Thumb instruction execution, validated across the full −40 °C to +85 °C industrial temperature range.

How much SRAM is accessible to the CPU on LPC2361FBD100?

LPC2361FBD100 provides 8 kB of SRAM directly on the ARM local bus for high-speed CPU access. Additionally, 16 kB of Ethernet buffer SRAM and 8 kB of USB/general-purpose DMA SRAM are accessible - though with higher latency than the local bus SRAM - and the 2 kB RTC SRAM remains available during power-down.

Can LPC2361FBD100 support USB host functionality?

No, LPC2361FBD100 supports only USB 2.0 device and OTG modes - not full USB host. USB host capability requires the LPC2364FBD100 or LPC2368FBD100 variants, which include additional USB host controller logic and descriptor handling firmware support beyond the base USB device stack present in LPC2361FBD100.

What analog input voltage range does the 10-bit ADC on LPC2361FBD100 support?

The 10-bit ADC on LPC2361FBD100 accepts analog inputs from 0 V to VREF, where VREF is externally supplied and typically tied to VDDA (3.3 V). The ADC uses a separate analog power domain (VDDA, VSSA) and reference pin (VREF) to ensure accuracy; absolute input must not exceed VDDA or fall below VSSA.