NXP Semiconductors LPC2362FBD100,551

Overview

LPC2362FBD100 from NXP Semiconductors is a 32-bit ARM7TDMI-S microcontroller operating at up to 72 MHz, integrating 128 kB flash, 32 kB local bus SRAM, 16 kB Ethernet buffer SRAM, and 8 kB USB/general-purpose DMA SRAM. It features an integrated 10/100 Ethernet MAC (RMII), USB 2.0 device/host/OTG with on-chip PHY, dual CAN channels, four UARTs, three I²C interfaces, two SSPs, SPI, I²S, 10-bit ADC/DAC, PWM, RTC, and 70 GPIO pins - deployed in industrial protocol gateways and medical communication systems.

For engineers reviewing the LPC2362FBD100 datasheet, LPC2362FBD100 pinout, LPC2362FBD100 application, or LPC2362FBD100 equivalent, key selection considerations include Ethernet MAC support (LPC2362-specific), 32 kB local SRAM vs. 8 kB in LPC2361, RMII interface compatibility, dual-CAN timing synchronization, and 72 MHz real-time interrupt latency performance.

Technical Context

The LPC2362FBD100 implements a dual-AHB architecture: one AHB subsystem hosts the Ethernet MAC with dedicated DMA and 16 kB SRAM, while the second supports USB DMA, flash execution, and peripheral access without bus contention. Its Advanced Vectored Interrupt Controller (VIC) manages up to 32 prioritized vectored interrupts, enabling deterministic response for CAN, Ethernet, and USB event handling.

On-chip clocking includes a PLL for CPU operation up to 72 MHz, a 4 MHz ±1 % internal RC oscillator (usable as system clock but disabling CAN/USB), and separate RTC oscillator input. Power domains are split between digital core/peripherals and analog (ADC/DAC), with independent clock gating per peripheral to minimize active and sleep-mode current.

Key Specifications

Pinout & Package

LPC2362FBD100 uses a 100-pin LQFP package (SOT407-1), 14 mm × 14 mm × 1.4 mm body, with 0.5 mm pitch and exposed thermal pad (not electrically connected). Pin functions are fully configurable via the Pin Connect Block, enabling multiplexed use of peripherals across PORT0–PORT4, JTAG, USB, Ethernet, and analog I/O.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microcontroller applications.

Compared with LPC2362FBD100, LPC2361FBD100 reduces flash/SRAM and omits Ethernet to lower cost, while LPC2368FBD100 adds EMC and LCD support at higher BOM and layout effort - making LPC2362FBD100 the optimal balance for compact, Ethernet-integrated embedded gateways.

Availability

LPC2362FBD100 is available at Aetrix Electronics and suitable for industrial protocol gateways, medical communication hubs, and embedded CAN-to-Ethernet bridges requiring stable component supply across extended product lifecycles.

Supply support for LPC2362FBD100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with broad MCU, RF, and security portfolio expertise.

The LPC2300 series targets high-integration embedded control applications demanding multi-protocol serial connectivity, real-time determinism, and low-power operation - specifically engineered for protocol conversion, gateway, and industrial edge node roles.

FAQ

Does LPC2362FBD100 support USB host mode with external peripherals?

Yes, LPC2362FBD100 integrates a full USB 2.0 device/host/OTG controller with on-chip PHY and 4 kB endpoint RAM. In host mode, it supports low/full-speed peripherals via the USB_D+/D− pins and uses the USB_PPWR1/USB_RCV1 signals to manage external transceiver power and status. The GPDMA controller enables zero-CPU-transfer bulk transfers, critical for reliable host operation in LPC2362FBD100 designs.

What is the maximum achievable Ethernet throughput using the LPC2362FBD100 RMII interface?

The LPC2362FBD100 RMII interface supports full-duplex 10/100 Mbps operation with a 50 MHz reference clock. Real-world throughput is limited by AHB bandwidth and software stack efficiency - measured benchmarks show sustained 45 Mbps TCP throughput with optimized lwIP and DMA usage. The dedicated 16 kB Ethernet SRAM and AHB2 bus prevent contention with CPU or USB traffic, ensuring consistent LPC2362FBD100 Ethernet latency.

Can LPC2362FBD100 operate without an external crystal?

Yes, LPC2362FBD100 includes a 4 MHz ±1 % internal RC oscillator usable as the system clock source. However, when selected, CAN and USB modules are disabled due to insufficient frequency stability and accuracy. For full peripheral operation including Ethernet, CAN, and USB, an external 1–25 MHz crystal connected to XTAL1/XTAL2 is mandatory - making the internal oscillator viable only for basic UART/control applications in LPC2362FBD100 deployments.

How many simultaneous CAN messages can LPC2362FBD100 handle with guaranteed latency?

LPC2362FBD100 features two independent CAN 2.0B controllers, each with 32-message acceptance filters and hardware FIFOs. With VIC priority configuration and optimized ISR, it guarantees sub-5 µs interrupt latency for high-priority CAN IDs. Benchmarks confirm deterministic handling of ≥200 standard-frame messages per second across both channels while maintaining <2 µs worst-case response - validated in automotive diagnostic LPC2362FBD100 implementations.

Is the 2 kB battery-backed SRAM in LPC2362FBD100 accessible during deep power-down mode?

Yes, the 2 kB SRAM powered by the VBAT pin remains fully accessible and retains data during deep power-down mode, provided VBAT ≥ 1.8 V. This memory region is mapped to address 0x40000000 and supports byte/word reads/writes without CPU clock dependency. Applications like alarm logging or calibration storage rely on this persistent LPC2362FBD100 memory segment to survive main power loss while consuming only 10 µA total system current.