NXP Semiconductors LPC2364FBD100,551
- Part No.:
- LPC2364FBD100,551
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
LPC2364FBD100,551.pdf
- Description:
- IC MCU 16/32B 128KB FLSH 100LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LPC2364FBD100 from NXP Semiconductors is a 32-bit ARM7TDMI-S microcontroller operating at up to 72 MHz, featuring 128 kB flash, 8 kB local SRAM, 16 kB Ethernet SRAM, dual CAN channels, and 10-bit ADC/DAC. It integrates Ethernet MAC (RMII), USB 2.0 full-speed device with on-chip PHY, four UARTs, two I²C buses, SPI/SSP, I²S, and 70 GPIOs - deployed in industrial gateways and protocol converters requiring deterministic real-time serial interface aggregation.
For engineers reviewing the LPC2364FBD100 datasheet, LPC2364FBD100 pinout, LPC2364FBD100 application, or LPC2364FBD100 equivalent, key selection criteria include RMII Ethernet support, dual-CAN capability, USB device + 4 kB FIFO, 2 kB battery-backed RTC SRAM, and LQFP100 package compatibility with legacy ARM7-based control designs.
Technical Context
The LPC2364FBD100 implements a dual-AHB architecture separating Ethernet DMA, USB DMA, and CPU instruction fetch to eliminate bus contention. Its Advanced Vectored Interrupt Controller supports 32 vectored IRQs with prioritized nesting, enabling low-latency response for CAN, Ethernet, and UART interrupt service routines.
It uses an on-chip PLL fed by a 1–24 MHz crystal or 4 MHz internal RC oscillator (±1 %) to generate the 72 MHz system clock. The 128-bit wide memory interface and accelerator architecture enable full 32-bit ARM instruction execution at peak frequency, delivering up to 30 % higher ISR performance than Thumb mode.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM7TDMI-S, 32-bit RISC, executes 32-bit instructions at up to 72 MHz |
| Flash Memory | 128 kB on-chip flash with ISP/IAP; accessible via ARM local bus for zero-wait-state execution |
| SRAM Allocation | 8 kB local SRAM (CPU bus), 16 kB Ethernet SRAM, 8 kB general-purpose/USB-accessible SRAM, 2 kB RTC-battery-backed SRAM |
| Serial Interfaces | 1× 10/100 Ethernet MAC (RMII), 1× USB 2.0 full-speed device (4 kB endpoint RAM), 4× UARTs, 2× CAN 2.0B controllers, 3× I²C, 2× SSP, 1× SPI, 1× I²S |
| Analog Peripherals | 10-bit ADC (6-channel multiplexed input), 10-bit DAC (single output AOUT), RTC with independent VBAT supply |
| Timers & PWM | 4× 32-bit general-purpose timers (8 capture, 10 compare), 1× PWM/timer block supporting three-phase motor control (6 outputs) |
| GPIO & Interrupts | 70 GPIO pins (Port 0–4), 12 external interrupt-capable pins (edge/level sensitive), VIC with 32 vectored IRQs |
Pinout & Package
LPC2364FBD100 is housed in a plastic LQFP100 package (SOT407-1), 14 mm × 14 mm × 1.4 mm body, with 100 leads and standard 0.5 mm pitch. Pin functions are configurable via the Pin Connect Block; all pins support digital I/O, and many offer multiple peripheral roles including Ethernet, USB, CAN, UART, I²C, SPI/SSP, I²S, ADC, DAC, and timer capture/match signals.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0[29]/USB_D+ | USB differential data line | Bi-directional D+ signal for USB 2.0 full-speed device operation; requires 1.5 kΩ pull-up resistor for enumeration |
| P0[30]/USB_D− | USB differential data line | Bi-directional D− signal; paired with P0[29] for noise-immune USB signaling per USB specification |
| P1[0]/ENET_TXD0 | Ethernet transmit data bit 0 | Part of RMII 2-bit parallel TX bus (with P1[1]); driven by MAC during packet transmission |
| P1[4]/ENET_TX_EN | Ethernet transmit enable | Active-high signal indicating valid data on ENET_TXD0/1; required for RMII physical layer synchronization |
| P1[9]/ENET_RXD0 | Ethernet receive data bit 0 | Part of RMII 2-bit RX bus (with P1[10]); sampled by MAC on rising edge of ENET_REF_CLK |
| P1[16]/ENET_MDC | MIIM management clock | Output clock for MDIO interface; used to configure external PHY registers (e.g., speed, duplex, link status) |
| P1[17]/ENET_MDIO | MIIM management data I/O | Open-drain bidirectional bus for reading/writing PHY registers over MDC clock |
| P0[26]/AOUT | DAC analog output | Single-ended 10-bit voltage output (0–VREF); requires external buffer for driving loads > 100 µA |
| P0[23]–P0[26]/AD0[0–3] | ADC input channels | Four of six 10-bit ADC inputs; share pins with I²S and UART3; require external anti-aliasing filtering |
| P1[30]/VBUS | USB bus power detect | Input monitoring USB VBUS presence; must be HIGH for USB reset and device enumeration to proceed |
Key Features
| Feature | Design Value |
|---|---|
| Dual-AHB subsystem | Enables concurrent Ethernet DMA, USB DMA, and CPU code execution without bus arbitration delay or throughput penalty |
| RMII Ethernet interface | Reduces PHY pin count and PCB routing complexity vs. MII; supports 10/100 Mbps with integrated MAC and 16 kB dedicated SRAM |
| USB 2.0 full-speed device | Includes on-chip transceiver and 4 kB endpoint RAM - eliminates need for external PHY and reduces BOM cost |
| Dual CAN 2.0B controllers | Supports simultaneous CAN FD-ready communication on two independent buses; each with message objects and acceptance filtering |
| Configurable pin function mapping | Pin Connect Block allows dynamic remapping of peripherals (e.g., UART0 to P2 instead of P0) without hardware change |
| Battery-backed RTC SRAM | 2 kB SRAM retains data during main power loss when VBAT is supplied; enables persistent logging and state retention |
Applications
| Industrial Protocol Gateway | Medical Data Aggregator |
|---|---|
Use Scenario: Translating Modbus RTU over RS-485 to EtherNet/IP or CANopen over industrial fieldbus. IC Role / Device Role / Timing Role: Central protocol conversion engine with deterministic UART/CAN/Ethernet scheduling and real-time packet buffering. Use Value: Dual CAN + RMII Ethernet + 4 UARTs enable direct bridging between three major industrial networks without external bridge ICs. |
Use Scenario: Collecting sensor data (ECG, SpO₂, temperature) from analog front-ends and transmitting securely over USB or Ethernet. IC Role / Device Role / Timing Role: Real-time data acquisition controller with synchronized ADC sampling, USB HID/COM-class streaming, and RTC timestamping. Use Value: Integrated 10-bit ADC, 10-bit DAC, USB device stack, and 2 kB battery-backed SRAM reduce component count and ensure data continuity during power transitions. |
| Automated Test Equipment Interface | Building Automation Controller |
Use Scenario: Controlling relay banks, reading digital I/O, and communicating with PC host via USB CDC or Ethernet TCP/IP. IC Role / Device Role / Timing Role: Embedded host controller managing high-speed GPIO toggling, precise PWM generation, and multi-protocol host interface. Use Value: 70 GPIOs with configurable pull-ups/downs, six PWM outputs, and USB/UART/Ethernet allow single-chip control of complex test fixtures. |
Use Scenario: Managing HVAC actuators, reading environmental sensors (I²C temp/humidity), and reporting via BACnet/IP or KNX over Ethernet. IC Role / Device Role / Timing Role: Field controller executing time-critical HVAC logic while maintaining network uptime and firmware updates over Ethernet. Use Value: RMII Ethernet with 16 kB SRAM ensures reliable BACnet/IP stack operation; I²C0/I²C1/I²C2 support multiple sensor buses on shared SCL/SDA lines. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC2366FBD100 | 256 kB flash, 32 kB local SRAM, same peripherals (dual CAN, USB, RMII Ethernet), identical pinout and package | Supports larger firmware images and more complex protocol stacks; no change to PCB or driver layer | Select when firmware size exceeds 128 kB or additional SRAM is needed for Ethernet/USB buffers |
| LPC2368FBD100 | 512 kB flash, 32 kB local SRAM, adds SD/MMC interface, same dual CAN, USB, RMII Ethernet, identical LQFP100 footprint | Enables local firmware update storage or data logging to microSD; requires minor PCB layout for SD card connector | Choose when field-upgradable firmware or buffered sensor data logging is required alongside full peripheral set |
Compared with LPC2364FBD100, LPC2366FBD100 offers double flash/SRAM for scalable firmware without layout changes, while LPC2368FBD100 adds SD/MMC support for local storage - both retain identical timing, interrupt structure, and peripheral register maps for drop-in software compatibility.
Availability
LPC2364FBD100 is available at Aetrix Electronics and suitable for industrial protocol gateways, medical data aggregators, and building automation controllers requiring stable component supply across extended product lifecycles.
Supply support for LPC2364FBD100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The LPC2364FBD100 belongs to the LPC2300 family of ARM7-based microcontrollers designed for high-integration, multi-serial-interface embedded control - targeting applications where Ethernet, USB, CAN, and analog peripherals must coexist on a single chip with deterministic real-time behavior.
FAQ
What is the maximum operating frequency of the LPC2364FBD100?
The LPC2364FBD100 operates at a maximum CPU clock frequency of 72 MHz, achieved using its on-chip PLL locked to an external 1–24 MHz crystal or the internal 4 MHz RC oscillator. This frequency applies to ARM7TDMI-S core execution, peripheral clocks, and bus interfaces - all fully specified and tested across the −40 °C to +85 °C industrial temperature range.
Does the LPC2364FBD100 support USB device functionality?
Yes, the LPC2364FBD100 integrates a USB 2.0 full-speed device controller with on-chip transceiver and 4 kB of dedicated endpoint RAM. It supports standard USB classes including CDC, HID, and MSC without requiring an external PHY. USB operation is confirmed for LPC2364FBD100 per NXP's LPC2364_65_66_67_68 datasheet Rev. 7.1.
How many CAN interfaces does the LPC2364FBD100 include?
The LPC2364FBD100 includes two independent CAN 2.0B controllers (CAN1 and CAN2), each supporting standard and extended frame formats, programmable bit timing, and message object buffers. This dual-CAN capability is explicitly documented for LPC2364FBD100 in Table 2 (Ordering Options) and Section 2 (Features and benefits) of the official datasheet.
What package type is used for the LPC2364FBD100?
The LPC2364FBD100 uses a plastic low-profile quad flat package (LQFP100) with 100 leads, body dimensions of 14 mm × 14 mm × 1.4 mm, and standard 0.5 mm lead pitch (SOT407-1). This package is pin-compatible with other members of the LPC236x series in LQFP100 format, including LPC2365FBD100 and LPC2366FBD100.
Is the LPC2364FBD100 compatible with RMII Ethernet PHYs?
Yes, the LPC2364FBD100 implements a full RMII (Reduced Media Independent Interface) compliant Ethernet MAC, supporting 10/100 Mbps operation with external PHYs such as the LAN8720A or DP83848. Its RMII interface includes ENET_TXD0/1, ENET_TX_EN, ENET_RXD0/1, ENET_CRS, ENET_RX_ER, ENET_REF_CLK, ENET_MDC, and ENET_MDIO - all mapped to dedicated LQFP100 pins per Table 3.
Does the LPC2364FBD100 include analog-to-digital and digital-to-analog converters?
Yes, the LPC2364FBD100 integrates a 10-bit successive-approximation ADC with six multiplexed input channels (AD0[0]–AD0[5]), and a 10-bit current-steering DAC with single output (AOUT on P0[26]). Both peripherals are fully functional and electrically characterized across the rated temperature range, with ADC reference selectable between VREF and AVDD.
LPC2364FBD100,551 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 100-LQFP
- Series:
- LPC2300
- Packaging:
- Tray
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Core Processor:
- ARM7®
- Core Size:
- 16/32-Bit
- Speed:
- 72MHz
- Connectivity:
- CANbus, Ethernet, I2C, Microwire, SPI, SSI, SSP, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, POR, PWM, WDT
- Number of I/O:
- 70
- Program Memory Size:
- 128KB (128K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 34K x 8
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 3.6V
- Data Converters:
- A/D 6x10b; D/A 1x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC2364FBD100,551 FAQ
1.How can I place an order for LPC2364FBD100,551 through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC2364FBD100,551 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC2364FBD100,551 reliable?
The price and inventory of LPC2364FBD100,551 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC2364FBD100,551 is usually 5 days.
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5.How can I obtain technical support or documentation for LPC2364FBD100,551?
For technical support, including LPC2364FBD100,551 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC2364FBD100,551 requirements.
6.How does Aetrix verify that LPC2364FBD100,551 is sourced from the original manufacturer or authorized distributors?
All LPC2364FBD100,551 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC2364FBD100,551 meets industry standards.
7.What is the process for return or replacement of LPC2364FBD100,551?
All LPC2364FBD100,551 units undergo pre-shipment inspection (PSI). If there is an issue with LPC2364FBD100,551, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC2364FBD100,551 part is unused and in its original packaging.
Return procedure for LPC2364FBD100,551:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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