NXP Semiconductors LPC2364FET100,518

Overview

LPC2364FET100 from NXP Semiconductors is a 32-bit ARM7TDMI-S microcontroller operating at up to 72 MHz, featuring 128 kB flash, 8 kB local SRAM, 16 kB Ethernet SRAM, and dual CAN channels. It integrates Ethernet MAC with RMII, USB 2.0 full-speed device interface with on-chip PHY, four UARTs, three I²C interfaces, I²S, SPI/SSP, 10-bit ADC (6-channel), 10-bit DAC, and 70 GPIO pins - deployed in industrial protocol converters and medical gateways.

For engineers reviewing the LPC2364FET100 datasheet, LPC2364FET100 pinout, LPC2364FET100 application, or LPC2364FET100 equivalent, key selection criteria include TFBGA100 package compatibility, dual-CAN + Ethernet coexistence, USB device operation without external PHY, and real-time interrupt handling via 32-vector VIC with 12 external interrupt-capable GPIOs.

Technical Context

The LPC2364FET100 implements a dual-AHB bus architecture separating Ethernet DMA, USB DMA, and CPU instruction fetch to eliminate bus contention. Its Advanced Vectored Interrupt Controller supports prioritized, low-latency response to up to 32 interrupts including timer match, UART FIFO, CAN message, and external edge/level-triggered sources.

On-chip peripherals are clock-gated individually for power optimization, and two independent power domains enable selective shutdown of Ethernet, USB, or analog subsystems. The 4 MHz internal RC oscillator (±1 %) serves as system clock source but disables CAN and USB - requiring external crystal (1–24 MHz) for full peripheral operation.

Key Specifications

Pinout & Package

Package: TFBGA100 (plastic thin fine-pitch ball grid array; 100 balls; body 9 × 9 × 0.7 mm; SOT926-1). Boundary-scan supported for PCB testability.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microcontroller applications.

Compared with LPC2364FET100, LPC2368FET100 provides scalable flash/SRAM for complex protocol stacks, while LPC2364FBD100 trades TFBGA density for LQFP manufacturability - neither offers pin-compatible replacement without layout revision due to differing land patterns and thermal pad requirements.

Availability

LPC2364FET100 is available at Aetrix Electronics and suitable for industrial protocol converters, medical data gateways, and embedded CAN-Ethernet bridges requiring stable component supply across extended product lifecycles.

Supply support for LPC2364FET100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.

The LPC2300 series targets resource-constrained embedded applications demanding integrated communication peripherals, real-time responsiveness, and long-term supply stability - particularly where Ethernet, USB, and CAN coexist in a single chip.

FAQ

What is the maximum operating frequency of the LPC2364FET100?

The LPC2364FET100 operates at a maximum CPU clock frequency of 72 MHz. This speed is achieved using the on-chip PLL, which can be driven by the main oscillator (1–24 MHz crystal), internal 4 MHz RC oscillator, or RTC oscillator. When using the internal RC oscillator, CAN and USB peripherals are disabled per datasheet specification.

Does the LPC2364FET100 support USB host functionality?

No, the LPC2364FET100 only implements a USB 2.0 full-speed device controller with on-chip PHY and 4 kB endpoint RAM. It does not support USB host or OTG modes. External USB host capability requires companion ICs such as the NXP ISP1583 or compatible USB host controllers.

How many CAN interfaces does the LPC2364FET100 include?

The LPC2364FET100 integrates two CAN 2.0B controllers (CAN1 and CAN2), confirmed in both the general description and Table 2 (Ordering Options). Each channel supports standard and extended frame formats, programmable bit timing, and message objects with acceptance filtering.

What is the purpose of the 2 kB battery-backed SRAM in the LPC2364FET100?

The 2 kB SRAM powered from the VBAT pin retains critical data (e.g., calibration values, event logs, configuration flags) during main power loss. It remains functional as long as VBAT ≥ 1.0 V and is accessible independently of the main power domain - essential for RTC timestamping and fail-safe state preservation in medical and industrial systems.

Is boundary-scan testing supported on the LPC2364FET100 package?

Yes, boundary-scan (IEEE 1149.1 JTAG) is supported on the LPC2364FET100 in its TFBGA100 package (SOT926-1), as explicitly stated in Section 2 ("Features and benefits") and confirmed in Table 1 (Ordering information). This enables automated PCB test coverage for solder joint integrity and interconnect verification.