NXP Semiconductors LPC2367FBD100,551

Overview

LPC2367FBD100 from NXP Semiconductors is a 32-bit ARM7TDMI-S microcontroller operating at up to 72 MHz, featuring 512 kB flash, 32 kB local SRAM, 16 kB Ethernet SRAM, and 8 kB USB/general-purpose DMA SRAM. It integrates Ethernet MAC with RMII, SD/MMC interface, four UARTs, three I²C buses, two SSPs, I²S, 10-bit ADC (6-channel), 10-bit DAC, PWM, RTC, and 70 GPIO pins - deployed in industrial protocol converters and embedded communication gateways.

For engineers reviewing the LPC2367FBD100 datasheet, LPC2367FBD100 pinout, LPC2367FBD100 application, or LPC2367FBD100 equivalent, key selection considerations include its 512 kB flash capacity, absence of on-chip USB PHY (unlike LPC2364/66/68), presence of SD/MMC support (LPC2367/68 only), RMII Ethernet interface, and LQFP100 package with 100-pin 0.5 mm pitch.

Technical Context

The LPC2367FBD100 implements a dual Advanced High-performance Bus (AHB) architecture enabling concurrent Ethernet DMA, program execution from flash, and general-purpose DMA without bus contention. Its AHB-to-APB bridge connects peripherals including the 10-bit ADC with six multiplexed inputs, 10-bit DAC output (P0[26]/AOUT), and Real-Time Clock with 2 kB battery-backed SRAM.

It supports Thumb/ARM instruction sets, with flash memory mapped on the ARM local bus for zero-wait-state access at 72 MHz. The device uses a PLL clocked by 1–24 MHz crystal or internal 4 MHz RC oscillator (±1 %), but USB operation requires external crystal - a constraint confirmed for LPC2367 due to lack of integrated USB PHY.

Key Specifications

Pinout & Package

LQFP100 package: 100-pin low-profile quad flat package with exposed thermal pad (SOT407-1), 0.5 mm lead pitch, 14 mm × 14 mm footprint, 1.4 mm max height. Pin functions are configurable via Pin Connect Block; all GPIO support pull-up/down resistors.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microcontroller applications.

Compared with LPC2368FBD100, LPC2367FBD100 trades integrated USB PHY for SD/MMC support and retains DAC - making it optimal for data-logging gateways. Against LPC2366FBD100, it doubles flash and adds DAC/SD/MMC at the expense of CAN, better serving storage- and analog-intensive designs.

Availability

LPC2367FBD100 is available at Aetrix Electronics and suitable for industrial protocol converters, embedded communication gateways, and medical data loggers requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant LQFP packaging.

Supply support for LPC2367FBD100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT applications.

The LPC2300 series was designed as a high-integration ARM7-based microcontroller family targeting multi-protocol embedded gateways - emphasizing Ethernet, serial interfaces, analog peripherals, and deterministic real-time performance in resource-constrained environments.

FAQ

Does LPC2367FBD100 include an integrated USB PHY?

No, LPC2367FBD100 does not include an on-chip USB PHY. Unlike LPC2364/66/68, it lacks USB_D+ and USB_D− transceiver circuitry. To implement USB device functionality, an external USB transceiver (e.g., NXP ISP1504) must be used with LPC2367FBD100's USB logic layer and 4 kB endpoint RAM. This is explicitly confirmed in the ordering options table and feature list.

What is the maximum operating frequency of LPC2367FBD100?

LPC2367FBD100 operates at a maximum CPU clock frequency of 72 MHz. This is achieved using the on-chip PLL, which can be driven by the 1–24 MHz crystal oscillator or the internal 4 MHz RC oscillator (±1 % accuracy). The 72 MHz rate applies to ARM/Thumb instruction execution on the local bus, with zero wait states for flash access under standard conditions.

Which peripherals are exclusive to LPC2367FBD100 within the LPC2364/65/66/67/68 family?

LPC2367FBD100 shares the SD/MMC interface exclusively with LPC2368FBD100 - neither LPC2364, LPC2365, nor LPC2366 support this feature. It also uniquely combines 512 kB flash, 32 kB local SRAM, RMII Ethernet, and 10-bit DAC in a single LQFP100 variant without USB PHY - a configuration not duplicated elsewhere in the family.

Can LPC2367FBD100 support CAN bus communication?

No, LPC2367FBD100 does not include a CAN controller. According to Table 2 (Ordering Options), the "CAN" column for LPC2367FBD100 is marked "–", confirming absence of CAN channels. In contrast, LPC2364/66/68 list "2" under CAN. This is consistent across all documentation - CAN is not implemented in the LPC2367 silicon.

What power supply requirements does LPC2367FBD100 have?

LPC2367FBD100 requires a single 3.3 V supply (operating range: 3.0 V to 3.6 V) for VDD(3V3), VDD(DCDC)(3V3), and digital I/O. It also needs separate analog supplies: VDDA and VSSA for ADC/DAC, with VREF referenced to VDDA. The RTC domain uses VBAT for backup power to retain 2 kB SRAM and RTC registers during main power loss.