NXP Semiconductors LPC2368FBD100,518
- Part No.:
- LPC2368FBD100,518
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
LPC2368FBD100,518.pdf
- Description:
- IC MCU 16/32B 512KB FLSH 100LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LPC2368FBD100 from NXP Semiconductors is a 32-bit ARM7TDMI-S microcontroller operating at up to 72 MHz, featuring 512 kB flash, 32 kB local SRAM, dual CAN channels, USB 2.0 full-speed device with on-chip PHY, and 10-bit ADC/DAC. It integrates Ethernet MAC with RMII, four UARTs, three I²C interfaces, I²S, SSP, SPI, SD/MMC controller, and 70 GPIO pins - deployed in industrial protocol gateways and medical communication systems.
For engineers reviewing the LPC2368FBD100 datasheet, LPC2368FBD100 pinout, LPC2368FBD100 application, or LPC2368FBD100 equivalent, key selection criteria include its dual-CAN + USB + Ethernet coexistence, 512 kB flash for complex firmware, RMII interface timing compliance, 3.3 V single-supply operation, and -40 °C to +85 °C industrial temperature range.
Technical Context
The LPC2368FBD100 implements a dual-AHB architecture separating Ethernet DMA, USB DMA, and CPU instruction fetch to eliminate bus contention. Its Advanced Vectored Interrupt Controller supports 32 vectored interrupts with configurable priority, enabling deterministic real-time response in multi-protocol gateway firmware.
It features an on-chip PLL for flexible clock generation (up to 72 MHz) from crystal, internal RC oscillator, or RTC source, and includes dedicated power domains for Ethernet, USB, and core logic to enable fine-grained power management across idle, sleep, power-down, and deep power-down modes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM7TDMI-S, 32-bit RISC, executes 32-bit instructions at up to 72 MHz |
| Flash Memory | 512 kB on-chip flash on ARM local bus for zero-wait-state execution |
| SRAM | 32 kB local SRAM (ARM bus), 16 kB Ethernet SRAM, 8 kB USB/GP DMA SRAM, 2 kB battery-backed RTC SRAM |
| Serial Interfaces | 1× 10/100 Ethernet MAC (RMII), 1× USB 2.0 full-speed device (4 kB FIFO), 4× UARTs, 2× CAN 2.0B, 3× I²C, 1× I²S, 2× SSP, 1× SPI, 1× SD/MMC |
| Analog Peripherals | 10-bit ADC (6-channel multiplexed input), 10-bit DAC (single output AOUT), RTC with separate VBAT supply |
| Timers & PWM | 4× 32-bit general-purpose timers (8 capture, 10 compare), 1× PWM unit supporting three-phase motor control (6 outputs) |
| GPIO & Interrupts | 70 GPIO pins with configurable pull-up/down; 12 external interrupt-capable pins (EINT0–EINT3 + Port 0/2 edge-sensitive) |
| Supply & Temp | Single 3.3 V supply (3.0 V–3.6 V); industrial temperature range: -40 °C to +85 °C |
Pinout & Package
LPC2368FBD100 uses a plastic LQFP100 package (SOT407-1), 14 mm × 14 mm × 1.4 mm body, with 100 leads and exposed thermal pad. Pin functions are highly multiplexed via the Pin Connect Block, enabling flexible peripheral routing without external logic.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0[29]/USB_D+ | USB differential pair | Full-speed USB 2.0 bidirectional data line; requires 36 Ω series termination and controlled-impedance PCB routing |
| P0[30]/USB_D− | USB differential pair | Complementary USB D− line; routed as matched-length pair with D+ for EMI compliance |
| P1[0]/ENET_TXD0 | Ethernet transmit data | Bit 0 of 4-bit RMII transmit bus; must meet setup/hold timing relative to ENET_TX_EN (P1[4]) |
| P1[4]/ENET_TX_EN | Ethernet transmit enable | Active-high strobe synchronizing RMII TXD[1:0] valid window; critical for PHY timing alignment |
| P1[9]/ENET_RXD0 & P1[10]/ENET_RXD1 | Ethernet receive data | 2-bit RMII receive bus; sampled on rising edge of ENET_REF_CLK (P1[15]); requires <2 ns skew |
| P0[23]/AD0[0] | ADC input channel 0 | Analog input for 10-bit successive-approximation ADC; referenced to VREF (pin E3), not VDDA |
| P0[26]/AOUT | DAC output | Single-ended 10-bit voltage output (0–VREF); no internal buffer - external op-amp required for driving loads |
Key Features
| Feature | Design Value |
|---|---|
| Dual-AHB subsystem | Enables concurrent Ethernet DMA, USB DMA, and flash execution without arbitration stalls - essential for real-time protocol bridging |
| On-chip USB PHY | Eliminates need for external transceiver; supports full-speed (12 Mbps) device mode only - no host capability |
| RMII Ethernet interface | Reduces pin count vs MII (5 vs 25 signals); requires 50 MHz reference clock (ENET_REF_CLK) sourced externally or from PLL |
| Two independent CAN controllers | Supports simultaneous CAN FD-ready (2.0B) networks - e.g., one for fieldbus, one for diagnostics or safety monitoring |
| Battery-backed 2 kB SRAM | Maintains critical state (e.g., calibration data, fault logs) during main power loss using VBAT pin and RTC domain isolation |
| Trace Clock & Packet pins | TRACECLK, TRACESYNC, and TRACEPKT[3:0] support real-time instruction trace via ARM CoreSight-compatible debug probes |
Applications
| Industrial Protocol Gateway | Medical Device Communication Hub |
|---|---|
Use Scenario: Aggregating Modbus RTU (RS-485), CANopen, and EtherNet/IP traffic into unified TCP/IP backbone. IC Role / Device Role / Timing Role: Central protocol translation engine with deterministic UART/CAN/ETH scheduling via VIC and GPDMA. Use Value: 512 kB flash stores multiple protocol stacks; dual CAN + Ethernet enables redundant fieldbus paths; RMII reduces PHY BOM cost by 30 %. |
Use Scenario: Interfacing infusion pumps, ECG monitors, and ventilators to hospital HL7/FHIR networks via wired Ethernet and USB diagnostic ports. IC Role / Device Role / Timing Role: Safety-critical data concentrator with isolated UARTs, battery-backed SRAM for audit logs, and USB for firmware updates. Use Value: 2 kB RTC SRAM retains patient event timestamps during power loss; USB device mode enables plug-and-play service tools; -40 °C to +85 °C rating supports sterilization cycles. |
| Multi-Interface Serial Converter | Embedded Control System |
Use Scenario: Converting RS-232/422/485 serial streams to TCP socket connections in SCADA remote terminal units (RTUs). IC Role / Device Role / Timing Role: High-throughput serial-to-Ethernet bridge with hardware FIFOs in all four UARTs and zero-copy GPDMA transfers. Use Value: Four UARTs with fractional baud rate generators support legacy equipment at non-standard rates (e.g., 38.4 kbps, 115.2 kbps); 72 MHz CPU handles TLS offload for secure MQTT. |
Use Scenario: Motion control in PLC-based packaging machinery requiring PWM-driven servo drives, analog sensor feedback (ADC), and real-time CAN coordination. IC Role / Device Role / Timing Role: Real-time motion controller with six PWM outputs, 10-bit ADC for current sensing, and CAN for distributed I/O synchronization. Use Value: Six-channel PWM unit supports three-phase BLDC commutation; 10-bit ADC achieves ±1 LSB INL for closed-loop current regulation; CAN controllers tolerate >10 kV ESD per ISO 11898-2. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC2478FBD208 | 208-pin LQFP; adds LCD controller, external memory interface (EMC), and enhanced USB OTG (host/device); same ARM7 core, 512 kB flash, but higher pin count and power | Targeted at HMI-enabled industrial panels; lacks LPC2368's optimized RMII layout and dual-CAN pin grouping | Select when external SDRAM or TFT display integration is required; avoid if board space or RMII signal integrity is constrained |
| LPC1769FBD100 | Cortex-M3 core (100 MHz), 512 kB flash, 64 kB RAM; adds Ethernet MAC with MII/RMII, USB Host/Device, but no on-chip USB PHY - requires external transceiver | Higher performance for C++/RTOS workloads; no native CAN FD readiness; different interrupt model (NVIC vs VIC) | Choose for new designs needing Cortex-M3 ecosystem compatibility; not drop-in due to register map, clock tree, and USB PHY differences |
Compared with LPC2478FBD208 and LPC1769FBD100, the LPC2368FBD100 delivers optimal balance of dual-CAN + USB + RMII in a compact 100-pin LQFP, with proven qualification for long-lifecycle industrial deployments where ARM7 toolchain stability and low-power Ethernet operation are prioritized over raw MIPS.
Availability
LPC2368FBD100 is available at Aetrix Electronics and suitable for industrial protocol gateways, medical communication hubs, and embedded control systems requiring stable component supply, extended lifecycle support, and qualified automotive-grade traceability.
Supply support for LPC2368FBD100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The LPC2300 series was designed specifically for high-integration, multi-protocol embedded control - emphasizing deterministic real-time performance, mixed-signal capability, and robust industrial I/O in a single-chip ARM7 solution.
FAQ
What is the maximum operating frequency of the LPC2368FBD100?
The LPC2368FBD100 operates at a maximum CPU clock frequency of 72 MHz, achieved via its on-chip PLL that multiplies input clock sources (crystal, internal RC, or RTC oscillator). This frequency is validated across the full -40 °C to +85 °C temperature range and 3.0 V–3.6 V supply, with all peripherals functional including dual CAN, USB, and Ethernet.
Does the LPC2368FBD100 include an on-chip USB transceiver?
Yes, the LPC2368FBD100 integrates a full-speed USB 2.0 device-mode transceiver with 4 kB endpoint RAM. Pins P0[29] (USB_D+) and P0[30] (USB_D−) are dedicated differential I/Os requiring 36 Ω series resistors and proper PCB impedance control. The transceiver does not support USB host mode or high-speed operation.
How many CAN controllers are implemented in the LPC2368FBD100?
The LPC2368FBD100 includes two independent CAN 2.0B controllers, each with full message object RAM and acceptance filtering. These are accessible via P0[1]/TD1/RXD3/SCL1 (CAN1) and P0[4]/I2SRX_CLK/RD2/CAP2[0] (CAN2), enabling simultaneous operation on separate CAN buses for redundancy or functional segregation.
What type of Ethernet interface does the LPC2368FBD100 support?
The LPC2368FBD100 implements a 10/100 Ethernet Media Access Controller (MAC) compliant with RMII v1.2. It requires an external PHY and uses pins P1[0]–P1[4], P1[8]–P1[10], P1[14]–P1[17], and P1[15] (ENET_REF_CLK) - supporting 50 MHz reference clock input and 2-bit nibble-wide data paths for minimal PCB layer count.
Is there battery-backed memory on the LPC2368FBD100?
Yes, the LPC2368FBD100 includes 2 kB of SRAM powered exclusively by the VBAT pin, which remains active during main power removal. This memory retains critical data such as calibration coefficients, fault logs, or security keys, and is accessible only through the RTC power domain - isolated from core reset events.
LPC2368FBD100,518 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 100-LQFP
- Series:
- LPC2300
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM7TDMI-S
- Core Size:
- 16/32-Bit
- Speed:
- 72MHz
- Connectivity:
- CANbus, Ethernet, FIFO, I2C, IrDA, MMC/SD/SDIO, SPI, SSP, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, POR, PWM, WDT
- Number of I/O:
- 70
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 58K x 8
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 3.6V
- Data Converters:
- A/D 6x10b SAR; D/A 1x10b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC2368FBD100,518 FAQ
1.How can I place an order for LPC2368FBD100,518 through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC2368FBD100,518 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC2368FBD100,518 reliable?
The price and inventory of LPC2368FBD100,518 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC2368FBD100,518 is usually 5 days.
3.What payment methods are accepted for LPC2368FBD100,518?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC2368FBD100,518 transactions.
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4.How is shipping managed for LPC2368FBD100,518?
LPC2368FBD100,518 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC2368FBD100,518 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC2368FBD100,518?
For technical support, including LPC2368FBD100,518 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC2368FBD100,518 requirements.
6.How does Aetrix verify that LPC2368FBD100,518 is sourced from the original manufacturer or authorized distributors?
All LPC2368FBD100,518 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC2368FBD100,518 meets industry standards.
7.What is the process for return or replacement of LPC2368FBD100,518?
All LPC2368FBD100,518 units undergo pre-shipment inspection (PSI). If there is an issue with LPC2368FBD100,518, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC2368FBD100,518 part is unused and in its original packaging.
Return procedure for LPC2368FBD100,518:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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