NXP Semiconductors LPC2368FBD100,551

Overview

LPC2368FBD100 from NXP Semiconductors is a 32-bit ARM7TDMI-S microcontroller operating at up to 72 MHz, featuring 512 kB flash, 32 kB local SRAM, dual CAN channels, USB 2.0 full-speed device interface with 4 kB endpoint RAM, and 10-bit ADC/DAC - deployed in industrial protocol gateways requiring deterministic serial bridging and real-time I/O control.

For engineers reviewing the LPC2368FBD100 datasheet, LPC2368FBD100 pinout, LPC2368FBD100 application, or LPC2368FBD100 equivalent, key selection criteria include RMII Ethernet support, dual-CAN timing synchronization, USB device stack readiness, 70 GPIO with edge/level interrupt capability, and 2 kB battery-backed RTC SRAM for state retention during power-down.

Technical Context

The LPC2368FBD100 integrates dual AHB buses enabling concurrent Ethernet DMA, USB DMA, and flash execution without bus contention; its Advanced Vectored Interrupt Controller supports 32 prioritized vectored interrupts with sub-12-cycle latency for hard real-time response in motor control and fieldbus protocols.

It implements a dual-clock domain architecture: one domain powers Ethernet, USB, and CAN peripherals with dedicated clock dividers, while the second manages CPU, memory, and low-power timers - enabling selective peripheral shutdown and deep power-down wake-up via RTC, USB activity, or external interrupts.

Key Specifications

Pinout & Package

LPC2368FBD100 uses a 100-pin LQFP package (SOT407-1), 14 mm × 14 mm × 1.4 mm body, with exposed thermal pad (not electrically connected). Pin functions are configurable via the Pin Connect Block, supporting multiplexed peripheral routing without external logic.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microcontroller applications.

Compared with LPC2366FBD100, the LPC2368FBD100 adds SD/MMC support and USB endpoint RAM for robust device-class firmware; versus LPC1769FBD100, it retains CAN 2.0B and simpler interrupt model but lacks Cortex-M3 features like bit-banding and SysTick calibration - making it preferable for legacy ARM7 toolchain continuity and CAN-centric industrial firmware.

Availability

LPC2368FBD100 is available at Aetrix Electronics and suitable for industrial protocol conversion, medical data acquisition, building automation, and embedded test equipment requiring stable component supply across extended product lifecycles.

Supply support for LPC2368FBD100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with roots in Philips Semiconductor.

The LPC2300 series was designed specifically for high-integration embedded networking applications - combining ARM7 real-time performance with rich serial connectivity (CAN, USB, Ethernet) and mixed-signal peripherals in a single-chip solution.

FAQ

What is the maximum operating frequency of the LPC2368FBD100?

The LPC2368FBD100 operates at a maximum CPU clock frequency of 72 MHz, achieved via an on-chip PLL that multiplies the input from the 1–24 MHz crystal oscillator or internal 4 MHz RC oscillator. The 72 MHz clock feeds the ARM7TDMI-S core, memory controllers, and most peripherals - though USB and CAN require the PLL output to be divided to meet their respective timing specifications.

Does the LPC2368FBD100 support both CAN 2.0A and CAN 2.0B protocols?

Yes, the LPC2368FBD100 integrates two fully compliant CAN 2.0B controllers supporting both standard (11-bit) and extended (29-bit) identifier formats, with programmable bit timing, message objects, and acceptance filtering. These controllers operate independently and can be used simultaneously for multi-bus diagnostics or redundancy in industrial networks.

Can the LPC2368FBD100 run USB and CAN concurrently?

Yes, the LPC2368FBD100 supports concurrent USB 2.0 full-speed device operation and dual CAN communication because its dual AHB bus architecture isolates USB DMA and CAN controller accesses from the CPU and flash bus. However, the internal 4 MHz RC oscillator cannot serve as the system clock when USB or CAN are active - a crystal oscillator (1–24 MHz) must be used.

What is the purpose of the 2 kB battery-backed SRAM in the LPC2368FBD100?

The 2 kB SRAM powered by the VBAT pin in the LPC2368FBD100 retains critical data (e.g., calibration coefficients, fault logs, security keys) during main power removal. It remains functional as long as VBAT ≥ 1.0 V, enabling reliable state preservation across power cycles - a requirement for medical devices complying with IEC 62304 and industrial systems needing fail-safe restart behavior.

How many GPIO pins on the LPC2368FBD100 support external interrupt capability?

The LPC2368FBD100 provides 12 dedicated external interrupt inputs (EINT0–EINT3 plus all Port 0 and Port 2 pins), with configurable edge/level sensitivity per pin. All 70 GPIO pins are individually controllable, but only those mapped to the VIC interrupt lines - including P0[0..31], P2[0..13], and P2[10..13] - can trigger interrupts in Power-down mode for wake-up events.