NXP Semiconductors LPC2368FET100,518

Overview

LPC2368FET100 from NXP Semiconductors is a 32-bit ARM7TDMI-S microcontroller operating at up to 72 MHz, featuring 512 kB flash, 32 kB local SRAM, dual CAN channels, USB 2.0 full-speed device interface with on-chip PHY, and 10-bit ADC/DAC - deployed in industrial protocol gateways requiring real-time serial bridging and deterministic interrupt response.

For engineers reviewing the LPC2368FET100 datasheet, LPC2368FET100 pinout, LPC2368FET100 application, or LPC2368FET100 equivalent, key selection criteria include RMII Ethernet support, TFBGA100 package compatibility, dual-CAN timing synchronization, USB device enumeration capability, and 70 GPIO with edge/level-sensitive interrupt routing across Ports 0–2.

Technical Context

The LPC2368FET100 implements a dual-AHB architecture separating Ethernet DMA, USB DMA, and CPU instruction fetch to eliminate bus contention during concurrent high-bandwidth peripheral operation. Its Advanced Vectored Interrupt Controller supports 32 prioritized vectored interrupts with sub-12-cycle latency for time-critical ISR execution.

It integrates dedicated hardware blocks including a 4-channel general-purpose DMA controller supporting SSP, I2S, and SD/MMC interfaces; a PWM unit with three-phase motor control logic; and independent power domains enabling selective peripheral clock gating and four low-power modes (idle, sleep, power-down, deep power-down).

Key Specifications

Pinout & Package

Package: TFBGA100 (plastic thin fine-pitch ball grid array; 100 balls; body 9 × 9 × 0.7 mm; SOT926-1). Ball pitch: 0.5 mm. Compatible with standard BGA reflow profiles and automated optical inspection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microcontroller applications.

Compared with LPC2478FET100 and LPC1769FBD100, the LPC2368FET100 uniquely balances dual-CAN timing precision, USB device + Ethernet coexistence, and battery-backed SRAM - making it irreplaceable in safety-critical protocol converters where deterministic dual-fieldbus synchronization and non-volatile fault logging are mandatory.

Availability

LPC2368FET100 is available at Aetrix Electronics and suitable for industrial protocol gateways, medical data aggregators, and automated test equipment requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant TFBGA packaging.

Supply support for LPC2368FET100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with headquarters in Eindhoven, Netherlands.

The LPC2300 series - including the LPC2368FET100 - was engineered specifically for multi-protocol industrial communication gateways, emphasizing deterministic real-time serial interface coexistence, low-latency interrupt handling, and robust operation across extended temperature ranges.

FAQ

What is the maximum operating frequency of the LPC2368FET100?

The LPC2368FET100 operates at a maximum CPU clock frequency of 72 MHz, achieved via its on-chip PLL that accepts input from the main crystal oscillator (1–24 MHz), internal 4 MHz RC oscillator, or RTC oscillator. This frequency is sustained across the full −40 °C to +85 °C industrial temperature range with single 3.3 V supply.

Does the LPC2368FET100 support both CAN 2.0A and CAN 2.0B protocols?

Yes, the LPC2368FET100 integrates two fully compliant CAN 2.0B controllers supporting both standard (11-bit) and extended (29-bit) identifier formats, with programmable bit timing, acceptance filtering, and message objects managed in on-chip RAM - confirmed in Section 12.2 of the LPC2364_65_66_67_68 datasheet Rev. 7.1.

Is the USB interface on the LPC2368FET100 a full-speed device only, or does it support host mode?

The LPC2368FET100 implements a USB 2.0 full-speed (12 Mbps) device-only interface with integrated PHY and 4 kB of dedicated endpoint RAM. It does not support USB host mode or high-speed operation - this is explicitly stated in the General Description and Table 2 (Ordering Options) of the official datasheet.

What is the purpose of the 2 kB battery-backed SRAM in the LPC2368FET100?

The 2 kB SRAM powered from the VBAT pin retains critical data (e.g., calibration coefficients, fault logs, security keys) during main power loss. It remains active as long as VBAT ≥ 1.0 V, enabling reliable state preservation in safety-critical applications such as medical devices or industrial controllers - detailed in Section 2 "Features and benefits" and Section 10.3 of the datasheet.

Can the LPC2368FET100's Ethernet MAC operate in MII mode, or is RMII the only supported interface?

The LPC2368FET100 Ethernet MAC supports RMII (Reduced Media Independent Interface) only - not full MII. Its pin allocation (P1[0], P1[1], P1[4], P1[9], P1[10], P1[14], P1[15], P1[16], P1[17]) matches the RMII specification, and the datasheet explicitly lists "RMII" under Ethernet column in Table 2 (Ordering Options) and Section 2 features.

How many general-purpose timers does the LPC2368FET100 include, and what are their key capabilities?

The LPC2368FET100 includes four 32-bit general-purpose timers (Timer 0–3), each with multiple capture inputs and match outputs. Timer 0 and 1 support quadrature encoder interface; Timer 2 and 3 offer up to four match registers per block. All timers feature external count inputs and operate independently of CPU load - specified in Section 2 "Features and benefits" and Chapter 17 of the user manual.