NXP Semiconductors LPC2917FBD144/01/,
- Part No.:
- LPC2917FBD144/01/,
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
LPC2917FBD144/01/,.pdf
- Description:
- IC MCU 16/32B 512KB FLSH 144LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:4,650
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC2917FBD144/01 from NXP Semiconductors is an ARM968E-S-based 32-bit microcontroller operating at up to 80 MHz, featuring dual CAN 2.0B controllers, two hardware LIN 2.0 masters, 512 kB on-chip flash, and 80 kB total RAM (including 16 kB ITCM + 16 kB DTCM + 48 kB SRAM). It targets automotive body control modules requiring real-time communication, deterministic interrupt response, and mixed-signal integration.
For engineers reviewing the LPC2917FBD144/01 datasheet, LPC2917FBD144/01 pinout, LPC2917FBD144/01 application, or LPC2917FBD144/01 equivalent, key selection considerations include CAN/LIN coexistence, 1.8 V core / 3.3 V I/O dual-supply operation, 144-pin LQFP package with 108 GPIOs, and support for in-system flash programming via CAN.
Technical Context
The LPC2917FBD144/01 implements a hierarchical clock architecture with independent base clocks (e.g., BASE_SYS_CLK, BASE_IVNSS_CLK, BASE_UART_CLK) routed through the Clock Generation Unit (CGU) and Power Management Unit (PMU), enabling per-peripheral clock gating and dynamic frequency scaling. Its AHB-to-APB bridges include write-ahead buffers to decouple CPU writes from peripheral timing.
It integrates two separate memory subsystems: tightly coupled memories (ITCM/DTCM) for low-latency code/data execution, and distributed SRAM blocks (32 kB + 16 kB) accessible via dedicated AHB slaves. The external static memory controller supports 32-bit data width and up to 24-bit addressing across eight banks.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM968E-S, 32-bit RISC, 5-stage pipeline, Thumb/ARM instruction set, 80 MHz max operation |
| Memory | 512 kB flash (in-system programmable via CAN/JTAG); 80 kB RAM (16 kB ITCM + 16 kB DTCM + 32 kB SRAM + 16 kB SRAM) |
| Communication | Two CAN 2.0B controllers with global acceptance filtering; two LIN 2.0 master interfaces with hardware protocol handling |
| Timers & PWM | Four 32-bit timers (each with four capture/compare registers); four 6-channel PWM units with trap and capture functions |
| Analog | Two 10-bit ADCs (16 total channels), 2.44 µs conversion time per channel, per-channel compare function to reduce interrupt load |
| I/O & Power | 108 GPIOs with configurable pull-up/pull-down/bus-keeper; 1.8 V ±5 % core supply; 2.7–3.6 V I/O supply; 5.5 V-tolerant inputs |
| Package | LQFP144 (SOT486-1), 20 × 20 × 1.4 mm body, −40 °C to +85 °C ambient operating range |
Pinout & Package
Package: LQFP144 (SOT486-1), plastic low-profile quad flat package with 144 leads, 20 mm × 20 mm body, 0.5 mm lead pitch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RST_N (Pin 73) | Asynchronous reset input | Active-low device reset; internally pulled up; initiates full system reset including peripherals and clock domains |
| VDD(CORE) (Pins 18, 60, 89, 127) | Digital core power supply | 1.8 V ±5 % supply for ARM968E-S core, TCMs, and AHB infrastructure; requires local decoupling |
| VDD(IO) (Pins 9, 31, 53, 82, 104, 131) | I/O power supply | 2.7–3.6 V supply for all GPIOs, UARTs, SPIs, CAN transceivers, and LIN drivers; enables 5.5 V-tolerant inputs |
| XIN_OSC / XOUT_OSC (Pins 76 / 75) | Cry stal oscillator interface | Connects to 10–25 MHz crystal; feeds PLL for CPU clock generation; requires external load capacitors |
| TDO / TDI / TMS / TCK / TRST_N / JTAGSEL (Pins 1, 144, 36, 37, 72, 108) | JTAG boundary-scan & debug interface | IEEE 1149.1-compliant test/debug port; JTAGSEL selects between ARM debug mode (LOW) and boundary-scan/flash programming (HIGH) |
| P0[0]/TXDC0 (Pin 93) & P0[1]/RXDC0 (Pin 95) | CAN0 differential transceiver interface | Dedicated CAN0 TX/RX pins with internal digital logic; require external CAN transceiver for physical layer compliance |
| P0[8]/TXDL0 & P0[9]/RXDL0 (Pins 112 / 113) | LIN0 master interface | Hardware LIN 2.0 master outputs; drive LIN bus directly via external LIN transceiver; support auto-baud and checksum generation |
Key Features
| Feature | Design Value |
|---|---|
| ARM968E-S with TCMs | 16 kB instruction TCM and 16 kB data TCM enable zero-wait-state execution of time-critical code and data, eliminating cache misses in safety-critical routines |
| Dual CAN + Dual LIN | Independent CAN 2.0B controllers and LIN 2.0 masters operate concurrently without shared resources, enabling multi-bus vehicle networks with synchronized message scheduling |
| Flexible clock domain isolation | CGU generates up to 10 base clocks; PMU controls >30 branch clocks individually-allowing selective peripheral clock gating to reduce dynamic power by >70 % in sleep modes |
| ADC with per-channel compare | Two 10-bit ADCs (16 channels total) include hardware comparators per channel, enabling threshold-triggered interrupts without CPU polling or firmware overhead |
| External Static Memory Controller | 32-bit data bus, 24-bit address bus, eight selectable banks-supports NOR flash, SRAM, and FPGA configuration memory with programmable wait states and burst modes |
Applications
| Body Control Module (BCM) | Powertrain Sensor Interface |
|---|---|
Use Scenario: Centralized control of door locks, lighting, wipers, and HVAC in modern automotive platforms. IC Role / Device Role / Timing Role: Primary MCU executing real-time LIN slave management, CAN gateway arbitration, and analog sensor acquisition. Use Value: Dual LIN masters directly manage up to 16 LIN nodes (e.g., mirror controls, seat modules); CAN controllers handle high-priority messages (e.g., brake status) with hardware filtering reducing CPU load by 40 %. | Use Scenario: Signal conditioning and communication interface for engine temperature, pressure, and throttle position sensors. IC Role / Device Role / Timing Role: Analog front-end processor with deterministic ADC sampling and CAN message formatting for ECU telemetry. Use Value: Two 10-bit ADCs acquire 16 sensor channels at 2.44 µs/channel; hardware compare triggers CAN alerts on out-of-range readings-eliminating software polling latency. |
| Industrial CAN Gateway | Smart Actuator Controller |
Use Scenario: Protocol translation between CANopen fieldbus and Modbus RTU over RS-485 in factory automation systems. IC Role / Device Role / Timing Role: Bridge MCU managing dual-CAN traffic, UART-to-CAN mapping, and firmware updates via CAN bootloader. Use Value: 512 kB flash stores dual application images (active/backup); in-system programming via CAN enables remote firmware updates without physical access or JTAG. | Use Scenario: Closed-loop motor control in HVAC dampers or robotic joints using PWM-driven H-bridges and current sensing. IC Role / Device Role / Timing Role: Real-time motion controller with synchronized PWM generation, ADC feedback capture, and LIN-based diagnostics. Use Value: Four 6-channel PWM units deliver 24 independent outputs; trap functionality halts PWM on overcurrent (via ADC input) within <1 µs-preventing MOSFET failure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NXP LPC2927FBD144 | Same ARM968E-S core, 768 kB flash, identical pinout and peripheral set; differs only in flash size | Requires no PCB change; suitable where larger firmware image or future feature expansion is needed | Select when >512 kB code space is required; otherwise LPC2917FBD144 offers optimal cost/performance balance |
| Renesas R7F0C004M2DFB | 16-bit RL78 core, 128 kB flash, single CAN, no LIN; 100-pin LQFP package | Lower performance, reduced communication capability, smaller footprint; not pin-compatible | Consider only for cost-sensitive, low-complexity LIN-only applications where CAN redundancy is unnecessary |
Compared with LPC2927FBD144, the LPC2917FBD144/01 saves cost and power in flash-constrained designs while retaining identical real-time capabilities; versus R7F0C004M2DFB, it delivers 3× higher CPU throughput, dual-CAN/LIN concurrency, and 4× more GPIOs-justifying its use in integrated vehicle network nodes.
Availability
LPC2917FBD144/01 is available at Aetrix Electronics and suitable for automotive body electronics, industrial CAN gateways, and smart actuator control requiring stable component supply, long-term lifecycle assurance, and AEC-Q100-aligned design-in support.
Supply support for LPC2917FBD144/01 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with leadership in ARM-based microcontrollers and automotive networking IP.
The LPC2900 series was designed specifically for automotive body electronics and industrial control systems requiring concurrent CAN and LIN communication, deterministic real-time response, and robust mixed-signal integration-all within a single-chip solution.
FAQ
What is the maximum operating frequency of the LPC2917FBD144/01?
The LPC2917FBD144/01 operates at a maximum CPU frequency of 80 MHz, achieved via its on-chip PLL driven by a 10–25 MHz crystal oscillator. This frequency applies to the ARM968E-S core, AHB system bus, and TCM interfaces. Peripheral clocks (e.g., UART, SPI, CAN) are derived independently via the CGU and may run at lower frequencies to optimize power consumption.
Does the LPC2917FBD144/01 support in-system programming via CAN?
Yes, the LPC2917FBD144/01 supports in-system programming (ISP) via CAN, as confirmed in Section 2.3 of the datasheet. This capability enables field firmware updates without JTAG hardware, using the built-in bootloader. The CAN interface must be configured in the application firmware to initiate ISP mode, and flash protection settings must permit external programming.
How many ADC channels does the LPC2917FBD144/01 provide, and what is their resolution and speed?
The LPC2917FBD144/01 integrates two independent 10-bit ADCs (ADC1 and ADC2), providing up to 16 total analog input channels. Each ADC achieves a minimum conversion time of 2.44 µs per channel. Both ADCs include per-channel hardware compare functionality to generate interrupts only when input values cross user-defined thresholds-reducing CPU polling overhead significantly.
What are the power supply requirements for the LPC2917FBD144/01?
The LPC2917FBD144/01 requires two distinct power supplies: a 1.8 V ±5 % supply (VDD(CORE)) for the ARM968E-S core, TCMs, and AHB infrastructure; and a 2.7–3.6 V supply (VDD(IO)) for all I/O pins, peripherals, and analog blocks. I/O pins are 5.5 V-tolerant, allowing direct interfacing with legacy 5 V logic without level shifters.
Is the LPC2917FBD144/01 pin-compatible with other devices in the LPC29xx family?
Yes, the LPC2917FBD144/01 shares identical pinout and package (LQFP144, SOT486-1) with the LPC2919FBD144 and LPC2927FBD144. All three devices are hardware-compatible at the board level; differences are limited to flash size (512 kB vs. 768 kB) and minor feature sets-enabling drop-in replacement during design-in or production ramp.
LPC2917FBD144/01/, Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 144-LQFP
- Series:
- LPC2900
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- ARM9®
- Core Size:
- 16/32-Bit
- Speed:
- 80MHz
- Connectivity:
- CANbus, EBI/EMI, LINbus, SPI, UART/USART
- Peripherals:
- POR, PWM, WDT
- Number of I/O:
- 108
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 80K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 16x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC2917FBD144/01/, FAQ
1.How can I place an order for LPC2917FBD144/01/, through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC2917FBD144/01/, on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC2917FBD144/01/, reliable?
The price and inventory of LPC2917FBD144/01/, are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC2917FBD144/01/, is usually 5 days.
3.What payment methods are accepted for LPC2917FBD144/01/,?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC2917FBD144/01/, transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC2917FBD144/01/,?
LPC2917FBD144/01/, orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC2917FBD144/01/, order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC2917FBD144/01/,?
For technical support, including LPC2917FBD144/01/, datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC2917FBD144/01/, requirements.
6.How does Aetrix verify that LPC2917FBD144/01/, is sourced from the original manufacturer or authorized distributors?
All LPC2917FBD144/01/, products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC2917FBD144/01/, meets industry standards.
7.What is the process for return or replacement of LPC2917FBD144/01/,?
All LPC2917FBD144/01/, units undergo pre-shipment inspection (PSI). If there is an issue with LPC2917FBD144/01/,, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC2917FBD144/01/, part is unused and in its original packaging.
Return procedure for LPC2917FBD144/01/,:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC2917FBD144/01/, Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

