NXP Semiconductors LPC2929FBD144,551
- Part No.:
- LPC2929FBD144,551
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
LPC2929FBD144,551.pdf
- Description:
- IC MCU 16/32B 768KB FLSH 144LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:2,789
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC2929FBD144 from NXP Semiconductors is an ARM968E-S-based microcontroller operating up to 125 MHz, featuring 768 kB flash, 56 kB SRAM + 2 × 32 kB TCM, dual CAN 2.0B controllers, two LIN 2.0 masters, full-speed USB 2.0 OTG, three 10-bit ADCs (24 total channels), and 104 GPIOs in a 144-pin LQFP package - deployed in industrial motor control and automotive body electronics.
For engineers reviewing the LPC2929FBD144 datasheet, LPC2929FBD144 pinout, LPC2929FBD144 application, or LPC2929FBD144 equivalent, key selection criteria include its dual-CAN/LIN/USB integration, 125 MHz ARM968E-S core with TCM architecture, 32-bit external memory interface, 5 V-tolerant analog inputs, and power management features enabling low-power embedded systems design.
Technical Context
The LPC2929FBD144 implements a multi-layer AHB bus at 125 MHz with four independent layers, supporting concurrent access to TCM, SRAM, flash, and peripherals. Its dual Clock Generation Units (CGU0/CGU1) provide independent clock scaling for CPU, USB, and peripheral domains, including fractional dividers and PLL-based frequency synthesis.
It integrates a dual-master GPDMA controller capable of memory-to-memory transfers and peripheral DMA (including TCM), alongside a configurable External Static Memory Controller (SMC) supporting eight banks, 32-bit data width, and 24-bit addressing - enabling direct connection to NOR/NAND flash, SRAM, and FPGA interfaces.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM968E-S, 32-bit RISC, up to 125 MHz - enables real-time deterministic execution with THUMB/ARM instruction set support. |
| Flash Memory | 768 kB on-chip flash - sufficient for complex firmware with bootloader, application, and field-upgradable code partitions. |
| RAM Configuration | 56 kB SRAM + 32 kB ITCM + 32 kB DTCM - TCM separation ensures zero-wait-state instruction/data access critical for interrupt latency and DSP routines. |
| ADC System | Three 10-bit ADCs: one 5 V-range (8 ch), two 3.3 V-range (16 ch total), 2.44 μs/channel - supports simultaneous sampling across motor current, temperature, and sensor monitoring. |
| Serial Interfaces | 2× CAN 2.0B, 2× LIN 2.0, USB 2.0 FS OTG, 2× UART (RS485-ready), 3× Q-SPI, 2× I²C - enables mixed-protocol vehicle network gateways and industrial HMI backplanes. |
| Package & Temp | LQFP144 (20 × 20 × 1.4 mm), −40 °C to +85 °C - suitable for extended-temperature industrial PCBs with standard reflow profiles. |
| Power Supply | Dual-rail: 1.8 V ±5 % (core), 2.7–3.6 V (I/O), 5.5 V tolerant inputs - simplifies power sequencing and allows direct interfacing with legacy 5 V sensors. |
Pinout & Package
144-pin LQFP (SOT486-1), 20 × 20 × 1.4 mm body, 0.5 mm pitch. Pin functions are multiplexed via SFSP registers in SCU; five GPIO ports (P0–P3, P5) provide 104 configurable I/Os with programmable pull-up/pull-down/bus keeper and 5 V tolerance on analog/digital pins.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD(CORE) | Digital core supply | 1.8 V ±5 % input - must be filtered separately from I/O rails to meet ARM968E-S noise immunity requirements. |
| VDD(IO) | I/O supply | 2.7–3.6 V rail powering GPIO, UART, SPI, and LIN transceivers - supports mixed-voltage system interfacing. |
| VDDA(ADC5V0) | Analog reference supply | 5 V dedicated supply for ADC0 - enables high-resolution measurement of 5 V sensor outputs without external level-shifting. |
| P0[24]/TXD1 | UART1 transmit | GPIO0 pin 24 default function - used for debug console or CAN gateway bridging; supports RS485 half-duplex via 9-bit mode. |
| P5[19]/USB_D+ | USB differential pair | Integrated USB PHY endpoint - eliminates need for external transceiver; requires 27 Ω series termination per line per USB spec. |
| RST | Asynchronous reset | Active-low, internally pulled up - must be held low ≥100 ns after power stabilization to ensure reliable boot initialization. |
Key Features
| Feature | Design Value |
|---|---|
| Dual CAN 2.0B controllers | FullCAN message RAM + global acceptance filtering - enables autonomous CAN node operation without host CPU intervention for priority arbitration. |
| Two LIN 2.0 master interfaces | Hardware LIN protocol engine with auto-sync-break detection - supports daisy-chained slave networks in automotive lighting and HVAC subsystems. |
| Configurable CGU with fractional dividers | Independent clock domains for CPU, USB, and peripherals - allows dynamic power scaling (e.g., reduce USB clock during idle while maintaining CAN timing). |
| Quadrature encoder interface (QEI) | Dedicated hardware for position/speed sensing - offloads motor control loop timing from CPU, reducing jitter in closed-loop servo applications. |
| ETB with 8 kB SRAM | Embedded Trace Buffer accessible as general-purpose RAM - enables real-time trace capture during debug while retaining application memory flexibility. |
Applications
| Industrial Motor Control | Automotive Body Electronics |
|---|---|
Use Scenario: Closed-loop BLDC motor drive with current sensing, thermal monitoring, and CAN-based command interface. IC Role / Device Role / Timing Role: Main system controller executing FOC algorithm, managing ADC sampling triggers, PWM generation, and CAN message scheduling. Use Value: Integrated 10-bit ADCs with sub-2.5 μs conversion and timer-triggered sampling enable precise current reconstruction; dual CAN handles motor command and diagnostics traffic concurrently. | Use Scenario: Central body control module coordinating door locks, window lifts, mirror controls, and interior lighting via LIN and CAN. IC Role / Device Role / Timing Role: Network gateway and actuator driver - LIN masters manage low-cost slave nodes; CAN interfaces communicate with BCM and instrument cluster. Use Value: Hardware LIN protocol acceleration reduces CPU load by >40 % vs software bit-banging; 5 V-tolerant GPIOs directly interface with legacy 5 V lock actuators. |
| Industrial HMI Gateway | Smart Energy Metering |
Use Scenario: Touchscreen HMI with local logic, serial connectivity to PLCs (RS485), and remote update via USB. IC Role / Device Role / Timing Role: Application processor running GUI stack, managing UART/RS485 communication, and hosting USB device firmware update interface. Use Value: 768 kB flash stores GUI assets, firmware, and configuration; USB OTG allows field technicians to perform secure firmware updates without disassembly. | Use Scenario: Polyphase energy meter with voltage/current sensing, tamper detection, and HAN communication via LIN/UART. IC Role / Device Role / Timing Role: Metrology controller acquiring synchronized ADC samples, computing RMS/kWh, and reporting via LIN to home area network. Use Value: Three independent ADCs allow simultaneous sampling of phase voltages and currents; built-in compare function reduces interrupt overhead for threshold-based tamper alerts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC2927FBD144 | 512 kB flash, identical peripheral set and pinout - differs only in flash capacity and part marking. | Same use cases but limited firmware complexity headroom; unsuitable for applications requiring >512 kB code+data. | Select when firmware size is confirmed ≤480 kB and cost optimization is prioritized over future scalability. |
| LPC2930FBD144 | Same package and core; adds Ethernet MAC, removes one LIN controller - not pin-compatible due to different peripheral mapping. | Suitable for wired industrial networking where Ethernet replaces LIN/CAN for backbone comms; requires PCB redesign. | Choose only if Ethernet connectivity is mandatory and LIN count reduction is acceptable; verify layout compatibility before migration. |
Compared with LPC2929FBD144, LPC2927FBD144 offers identical performance and peripherals but less flash for cost-sensitive deployments, while LPC2930FBD144 trades LIN capability for Ethernet - making LPC2929FBD144 optimal for mixed-protocol automotive and industrial gateways requiring maximum non-volatile storage and dual-LIN support.
Availability
LPC2929FBD144 is available at Aetrix Electronics and suitable for industrial motor control, automotive body electronics, and smart energy metering requiring stable component supply across long-lifecycle production programs.
Supply support for LPC2929FBD144 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The LPC2900 series was designed specifically for automotive and industrial applications demanding robust mixed-signal integration, real-time communication (CAN/LIN/USB), and deterministic ARM9 performance in extended temperature environments.
FAQ
What is the maximum operating frequency of the LPC2929FBD144?
The LPC2929FBD144 operates at a maximum CPU frequency of 125 MHz, achieved via its on-chip PLL with input range 10–25 MHz. This frequency applies to the ARM968E-S core and associated AHB bus; peripheral clocks (e.g., USB, CAN) are derived independently through CGU0/CGU1 fractional dividers to maintain timing compliance.
Does the LPC2929FBD144 support USB device and host functionality?
The LPC2929FBD144 integrates a full-speed USB 2.0 OTG controller with on-chip PHY, supporting device, host, and OTG roles. It includes a dedicated USB DMA controller and supports standard USB classes (CDC, HID, MSC) - however, host-mode operation requires external VBUS detection and power switching circuitry per USB specification.
How many analog input channels does the LPC2929FBD144 support?
The LPC2929FBD144 provides 24 analog input channels across three independent 10-bit ADCs: ADC0 (8 channels, 5 V range), ADC1 (8 channels, 3.3 V range), and ADC2 (8 channels, 3.3 V range). Each ADC supports hardware compare functions and multiple trigger sources (timer, PWM, external signal) to minimize CPU interrupt load.
Is the LPC2929FBD144 pin-compatible with other LPC29xx variants?
The LPC2929FBD144 shares the same LQFP144 package and pin assignment with LPC2926FBD144 and LPC2927FBD144 - all are fully pin-compatible. However, it is not pin-compatible with LPC291x series due to reduced MSCSS/timer pinout and differing peripheral mappings, requiring PCB redesign for migration.
What power supply rails are required for the LPC2929FBD144?
The LPC2929FBD144 requires three primary supply rails: 1.8 V ±5 % for the digital core (VDD(CORE)), 2.7–3.6 V for I/O (VDD(IO)), and dedicated analog supplies - 3.3 V (VDDA(ADC3V3)) and 5 V (VDDA(ADC5V0)) for ADC references. Separate decoupling capacitors per rail and proper ground partitioning are mandatory for stable operation.
LPC2929FBD144,551 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 144-LQFP
- Series:
- LPC2900
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- ARM9®
- Core Size:
- 16/32-Bit
- Speed:
- 125MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, LINbus, SPI, UART/USART, USB
- Peripherals:
- DMA, POR, PWM, WDT
- Number of I/O:
- 104
- Program Memory Size:
- 768KB (768K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 16K x 8
- RAM Size:
- 56K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 24x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC2929FBD144,551 FAQ
1.How can I place an order for LPC2929FBD144,551 through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC2929FBD144,551 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC2929FBD144,551 reliable?
The price and inventory of LPC2929FBD144,551 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC2929FBD144,551 is usually 5 days.
3.What payment methods are accepted for LPC2929FBD144,551?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC2929FBD144,551 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC2929FBD144,551?
LPC2929FBD144,551 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC2929FBD144,551 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC2929FBD144,551?
For technical support, including LPC2929FBD144,551 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC2929FBD144,551 requirements.
6.How does Aetrix verify that LPC2929FBD144,551 is sourced from the original manufacturer or authorized distributors?
All LPC2929FBD144,551 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC2929FBD144,551 meets industry standards.
7.What is the process for return or replacement of LPC2929FBD144,551?
All LPC2929FBD144,551 units undergo pre-shipment inspection (PSI). If there is an issue with LPC2929FBD144,551, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC2929FBD144,551 part is unused and in its original packaging.
Return procedure for LPC2929FBD144,551:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC2929FBD144,551 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

