NXP Semiconductors LPC4317JET100E
- Part No.:
- LPC4317JET100E
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 100-TFBGA
- Datasheet:
-
LPC4317JET100E.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 100TFBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LPC4317JET100E from NXP Semiconductors is a dual-core ARM Cortex-M4F/M0 microcontroller targeting industrial control and embedded connectivity applications. It delivers 204 MHz CPU performance, 1 MB flash (512 kB per bank), 136 kB SRAM, no Ethernet or LCD controller, and supports USB Host/Device (no OTG) and C_CAN 2.0B - deployed in motor drives and smart metering systems.
For engineers reviewing the LPC4317JET100E datasheet, LPC4317JET100E pinout, LPC4317JET100E application, or LPC4317JET100E equivalent, key selection criteria include its TFBGA100 package, -40 °C to +105 °C operating range, absence of Ethernet/LCD, and dedicated C_CAN and SD/MMC interfaces for deterministic real-time communication and data logging.
Technical Context
The LPC4317JET100E integrates an ARM Cortex-M4F core with hardware FPU and MPU alongside an ARM Cortex-M0 coprocessor, enabling asymmetric multiprocessing: the M4 handles compute-intensive tasks (e.g., motor control algorithms), while the M0 offloads peripheral management and real-time I/O handling. Both cores operate up to 204 MHz and share access to on-chip memory via AHB multilayer matrix.
Its peripheral set includes two 10-bit ADCs (400 kSamples/s, 4 channels total), one 10-bit DAC, quad SPI Flash Interface (SPIFI), two SSP controllers, one SPI, two I2S, Fast-mode Plus I²C, and C_CAN 2.0B - all accessible through the Global Input Multiplexer Array (GIMA) for flexible event routing to timers, SCTimer/PWM, or ADCs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: ARM Cortex-M4F (204 MHz, FPU, MPU) + ARM Cortex-M0 (204 MHz, co-processor) |
| Memory | 1 MB flash (dual-bank, 512 kB each), 136 kB SRAM, 16 kB EEPROM, 64 kB ROM boot code |
| Analog Peripherals | Two 10-bit ADCs (400 kSamples/s, 4 input channels total), one 10-bit DAC (400 kSamples/s) |
| Connectivity | No Ethernet or LCD; one High-speed USB 2.0 Host/Device (ULPI interface only), one C_CAN 2.0B controller |
| Digital Interfaces | SPIFI (quad SPI, 52 MB/s), two SSP, one SPI, two I2S, Fast-mode Plus I²C (1 Mbit/s), SD/MMC interface |
| Package & Temp | TFBGA100 (9 × 9 × 0.7 mm), industrial temperature range: -40 °C to +105 °C |
| Power | Single 3.3 V supply (2.4–3.6 V), four low-power modes (Sleep, Deep-sleep, Power-down, Deep power-down) |
Pinout & Package
Package: TFBGA100 (SOT926-1), plastic thin fine-pitch ball grid array, 100 balls, 0.5 mm pitch, body size 9 mm × 9 mm × 0.7 mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0_0 | GPIO / SSP1_MISO / I2S0_TX_WS | Multi-function digital I/O; supports master/slave SPI, I2S word select, or general-purpose use with SCU configuration |
| P1_7 | GPIO1[0] / USB0_PPWR / EMC_D0 | USB VBUS drive control (active HIGH); also serves as external memory data line 0 or GPIO |
| P1_9 | GPIO1[2] / U1_RTS / SD_DAT0 | UART1 RTS output or SD card data line 0 - enables shared pin usage between serial comms and storage interface |
| P1_12 | GPIO1[5] / T0_CAP1 / SD_DAT3 | Capture input for Timer 0 or SD bus line 3 - supports encoder feedback or memory card read/write |
| P1_15 | GPIO0[2] / U2_TXD / ENET_RXD0 | USART2 transmit or Ethernet RX data - unused in LPC4317JET100E due to no Ethernet; defaults to GPIO/USART |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core asymmetry | M4F handles real-time computation (e.g., field-oriented motor control); M0 manages USB/CAN protocol stacks and GPIO interrupts without M4 intervention |
| GIMA event routing | Enables dynamic cross-connection of 32+ inputs (ADC triggers, timer events, GPIO edges) to 16+ peripherals - eliminates software polling overhead |
| SCTimer/PWM subsystem | State-configurable timer with match/capture logic and PWM generation - supports complex waveform synthesis for multi-phase inverters |
| Secure boot & OTP | 64-bit + 256-bit One-Time Programmable memory stores cryptographic keys or calibration data; ROM bootloader enforces secure firmware validation |
| Low-power RTC domain | 256 bytes of battery-backed registers + alarm timer - maintains timekeeping and wake-up capability during Deep power-down mode |
Applications
| Industrial Motor Control | Smart Energy Metering |
|---|---|
|
Use Scenario: Closed-loop three-phase BLDC motor control in HVAC compressors or pump drives requiring precise timing and analog feedback. IC Role / Device Role / Timing Role: Primary controller executing FOC algorithm on Cortex-M4F; Cortex-M0 handles CAN messaging and ADC sampling synchronization. Use Value: Dual-core isolation ensures deterministic PWM timing (<100 ns jitter) while maintaining CAN FD-compliant communication at 1 Mbps. |
Use Scenario: DIN-rail mounted electricity meter with tariff switching, tamper detection, and remote firmware updates over CAN bus. IC Role / Device Role / Timing Role: Main MCU managing metrology ADC sampling, EEPROM-based tariff tables, and C_CAN 2.0B communication stack. Use Value: 10-bit dual ADC (400 kSamples/s) captures voltage/current waveforms simultaneously; 16 kB EEPROM stores calibration and billing history securely. |
| RFID Reader Terminal | White Goods Control Unit |
|
Use Scenario: ISO14443-A/B contactless reader for access control systems with anti-collision and secure authentication. IC Role / Device Role / Timing Role: Host processor interfacing with RFID transceiver IC via SPIFI or SSP; manages crypto acceleration via ROM-based drivers. Use Value: SPIFI executes firmware directly from external QSPI flash; Fast-mode Plus I²C configures transceiver registers at 1 Mbit/s for rapid command response. |
Use Scenario: Washing machine main control board coordinating drum motor, water valves, heater, and user interface with fault diagnostics. IC Role / Device Role / Timing Role: Central MCU running real-time state machine; uses SCTimer/PWM for motor phase control and GPIO group interrupts for door lock sensing. Use Value: Eight-channel GPIO group interrupt detects multi-pin patterns (e.g., lid open + water level low) in single cycle - reduces BOM by eliminating external logic. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC4337JET100 | Includes Ethernet MAC (10/100T) and second USB port with OTG support; same flash/SRAM, identical TFBGA100 package | Required for networked gateways or devices needing IEEE 1588 time stamping; adds PHY interface complexity and BOM cost | Select when Ethernet connectivity or USB OTG host capability is mandatory; otherwise, LPC4317JET100 reduces system cost and layout area |
| LPC4327JET100 | Removes Ethernet and LCD; retains USB Host/Device and C_CAN; reduced flash (1 MB → 768 kB), same SRAM and TFBGA100 | Suitable for cost-sensitive industrial sensors where full 1 MB flash is unnecessary but USB/CAN coexistence is critical | Choose for lower-cost deployments where firmware footprint fits within 768 kB; LPC4317JET100 offers larger flash margin for future feature expansion |
Compared with LPC4337JET100 and LPC4327JET100, the LPC4317JET100 provides identical dual-core architecture and peripheral count except Ethernet and LCD - making it optimal for CAN/USB-based control nodes where network stack overhead and PHY components are unnecessary.
Availability
LPC4317JET100E is available at Aetrix Electronics and suitable for industrial motor control, smart metering, RFID reader terminals, and white goods control units requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for LPC4317JET100E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in ARM-based microcontrollers and edge processing.
The LPC43xx family was designed for high-integration industrial control applications demanding dual-core determinism, rich analog/mixed-signal capability, and robust communication interfaces - with LPC4317JET100E optimized for CAN/USB-centric systems without Ethernet overhead.
FAQ
What is the maximum operating frequency of the LPC4317JET100E?
The LPC4317JET100E supports CPU operation up to 204 MHz on both the ARM Cortex-M4F and Cortex-M0 cores. This frequency is achieved using internal PLLs that allow full-speed operation without requiring an external high-frequency crystal oscillator - simplifying clock tree design while maintaining timing precision for real-time control loops.
Does the LPC4317JET100E include Ethernet or LCD controller functionality?
No, the LPC4317JET100E does not include Ethernet MAC or LCD controller hardware. These peripherals are explicitly omitted per the ordering table in the datasheet - distinguishing it from higher-tier variants like LPC4357 or LPC4337. Designers must implement external connectivity or display interfaces if required.
How many ADC channels are available on the LPC4317JET100E?
The LPC4317JET100E integrates two independent 10-bit ADCs (ADC0 and ADC1), with a combined total of four input channels. Each ADC supports up to four dedicated or multiplexed inputs, and both share common channel numbering (e.g., ADC0_0 and ADC1_0 are tied together), enabling simultaneous sampling for differential or redundant measurements.
What USB capabilities does the LPC4317JET100E support?
The LPC4317JET100E features one High-speed USB 2.0 Host/Device interface with DMA support and an on-chip full-speed PHY, plus ULPI interface support for connecting to external high-speed PHYs. It does not support USB OTG or the second USB port found in LPC435x/3x variants - limiting it to single-role USB implementations.
Is the LPC4317JET100E pin-compatible with other LPC43xx TFBGA100 variants?
Yes, the LPC4317JET100E shares identical pinout and package (TFBGA100, SOT926-1) with other LPC43xx family members in the same footprint, including LPC4333JET100, LPC4327JET100, and LPC4337JET100. Signal mapping is consistent across variants, enabling hardware reuse when migrating between models with differing peripheral sets.
LPC4317JET100E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 100-TFBGA
- Series:
- LPC43xx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M4/M0
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 204MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, IrDA, Microwire, SD, SPI, SSI, SSP, UART/USART
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, POR, WDT
- Number of I/O:
- 49
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 16K x 8
- RAM Size:
- 136K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.2V ~ 3.6V
- Data Converters:
- A/D 4x10b; D/A 1x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC4317JET100E FAQ
1.How can I place an order for LPC4317JET100E through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC4317JET100E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC4317JET100E reliable?
The price and inventory of LPC4317JET100E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC4317JET100E is usually 5 days.
3.What payment methods are accepted for LPC4317JET100E?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC4317JET100E transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC4317JET100E?
LPC4317JET100E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC4317JET100E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC4317JET100E?
For technical support, including LPC4317JET100E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC4317JET100E requirements.
6.How does Aetrix verify that LPC4317JET100E is sourced from the original manufacturer or authorized distributors?
All LPC4317JET100E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC4317JET100E meets industry standards.
7.What is the process for return or replacement of LPC4317JET100E?
All LPC4317JET100E units undergo pre-shipment inspection (PSI). If there is an issue with LPC4317JET100E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC4317JET100E part is unused and in its original packaging.
Return procedure for LPC4317JET100E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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