NXP Semiconductors LPC4337JET256Y
- Part No.:
- LPC4337JET256Y
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 256-LBGA
- Datasheet:
-
LPC4337JET256Y.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 256LBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LPC4337JET256Y from NXP Semiconductors is a dual-core ARM Cortex-M4F/M0 microcontroller with 1 MB flash, 136 kB SRAM, and integrated Ethernet MAC, dual high-speed USB 2.0 interfaces, and C_CAN 2.0B controllers - designed for industrial automation and motor control systems requiring real-time determinism and peripheral offload.
For engineers reviewing the LPC4337JET256Y datasheet, LPC4337JET256Y pinout, LPC4337JET256Y application, or LPC4337JET256Y equivalent, key selection criteria include its LBGA256 package, -40 °C to +105 °C extended temperature grade, absence of LCD controller (vs. LPC435x), and dual-core debug support via JTAG/SWD.
Technical Context
The LPC4337JET256Y implements a tightly coupled dual-core architecture: the Cortex-M4F core runs at up to 204 MHz with hardware FPU and MPU, while the Cortex-M0 coprocessor operates at up to 204 MHz to handle peripheral management and interrupt servicing - enabling deterministic real-time response without CPU contention. Both cores share access to AHB peripherals including the State Configurable Timer (SCTimer/PWM) and Global Input Multiplexer Array (GIMA).
It integrates two independent high-speed USB 2.0 controllers - one with on-chip HS PHY (USB0), the other with ULPI interface for external HS PHY (USB1) - alongside a 10/100T Ethernet MAC with IEEE 1588-2008 v2 timestamping support, and an External Memory Controller (EMC) supporting SDRAM, NOR flash, and SRAM expansion.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | ARM Cortex-M4F @ 204 MHz + Cortex-M0 @ 204 MHz; enables real-time task partitioning and peripheral offload without inter-core bus contention. |
| Memory | 1 MB dual-bank flash (512 kB per bank), 136 kB SRAM, 16 kB EEPROM; supports XIP from SPIFI and background flash reprogramming. |
| Connectivity | 10/100T Ethernet MAC with RMII/MII and IEEE 1588 v2 timestamping; dual USB 2.0 (one with on-chip HS PHY, one with ULPI). |
| Analog Peripherals | Two 10-bit ADCs (400 kSamples/s, 8 channels each); one 10-bit DAC (400 kSamples/s); enables closed-loop analog sensing and actuation. |
| Digital I/O | 164 GPIO pins with configurable pull-up/down, DMA-capable ports, and eight GPIO group interrupts; supports fast event-driven I/O handling. |
| Package & Temp | LBGA256 (17 × 17 × 1 mm, SOT740-2); rated for -40 °C to +105 °C industrial operation - suitable for harsh ambient environments. |
Pinout & Package
Package: LBGA256 (Plastic low profile ball grid array; 256 balls; body 17 × 17 × 1 mm; SOT740-2). Pin functions are defined per the official NXP LPC43xx pin description table for LBGA256, with multiplexed digital I/O supporting up to eight alternate functions per pin via SCU configuration.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0_0 | GPIO0[0] / SSP1_MISO / ENET_RXD1 | Primary use as general-purpose I/O; also serves as Ethernet receive data line 1 in RMII/MII mode - critical for compact Ethernet PHY interfacing. |
| P1_15 | GPIO0[2] / ENET_RXD0 / T0_MAT1 | Combines Ethernet RX data line 0 with timer match output - enables synchronized timing capture during network packet reception. |
| P1_18 | GPIO0[13] / ENET_TXD0 / T0_MAT3 | Provides Ethernet transmit data line 0 and timer match output - allows precise waveform generation concurrent with Ethernet transmission. |
| P1_19 | ENET_TX_CLK / SSP1_SCK / CLKOUT | Shared Ethernet reference clock (RMII) and serial clock source - simplifies clock tree design when using both Ethernet and SSP peripherals. |
| P1_20 | GPIO0[15] / SSP1_SSEL | Slave select for SSP1; configurable as GPIO - essential for daisy-chained SPI flash or sensor interfaces with chip-select arbitration. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core asymmetric processing | Cortex-M4F handles compute-intensive tasks (e.g., motor FOC, audio codec), while Cortex-M0 manages USB/Ethernet stack and GPIO interrupts - reducing M4F load by ~40 % in benchmarked industrial firmware. |
| State Configurable Timer (SCTimer) | Hardware state machine with 16 input events and 16 outputs; enables complex PWM patterns (e.g., 3-phase BLDC commutation) without CPU intervention or timer resource conflict. |
| Global Input Multiplexer Array (GIMA) | Routes 32+ peripheral inputs (ADC triggers, timer captures, CAN edges) to any of 16 event-driven peripherals - eliminates software polling and reduces latency to <100 ns. |
| IEEE 1588-2008 v2 Ethernet timestamping | Hardware timestamp insertion into PTP frames at MAC layer; achieves sub-100 ns time synchronization accuracy for distributed control networks. |
| Quad SPI Flash Interface (SPIFI) | 4-lane interface supporting execute-in-place (XIP) from external QSPI flash at up to 52 MB/s - replaces parallel NOR flash, saving PCB area and BOM cost. |
Applications
| Industrial Motor Control | Smart Energy Metering |
|---|---|
Use Scenario: Closed-loop field-oriented control (FOC) of 3-phase AC induction motors in HVAC compressors and pump drives. IC Role / Device Role / Timing Role: LPC4337JET256Y executes FOC algorithm on Cortex-M4F while Cortex-M0 manages encoder QEI, PWM dead-time insertion, and fault monitoring via SCTimer. Use Value: Achieves 20 kHz PWM switching with <500 ns jitter and real-time current sampling at 400 kSamples/s - meeting IEC 61800-3 EMC and SIL-2 functional safety requirements. | Use Scenario: Polyphase electricity meter with tariff switching, tamper detection, and DLMS/COSEM protocol over PLC or RF. IC Role / Device Role / Timing Role: Cortex-M4F processes metrology algorithms (RMS, harmonics) from dual 10-bit ADCs; Cortex-M0 handles secure communication stacks (AES-128, TLS) and RTC-based billing intervals. Use Value: On-chip 16 kB EEPROM stores calibration coefficients and tamper logs; IEEE 1588 sync enables phase-coherent sampling across multi-meter deployments. |
| Industrial Ethernet Gateway | RFID Reader Controller |
Use Scenario: Protocol translation between Modbus RTU (RS-485) and EtherNet/IP or PROFINET in factory floor gateways. IC Role / Device Role / Timing Role: Ethernet MAC with hardware timestamping handles real-time frame scheduling; dual USB supports firmware update and diagnostic tools; EMC enables local HMI display memory mapping. Use Value: Dual-core isolation prevents communication stack stalls from affecting real-time I/O scanning - achieving <1 ms cycle times at 100 Mbps line rate. | Use Scenario: UHF RFID reader for asset tracking in logistics, supporting ISO 18000-6C and EPC Gen2 protocols with anti-collision. IC Role / Device Role / Timing Role: Cortex-M4F modulates RF carrier and decodes backscatter signals; Cortex-M0 manages GPIO-triggered antenna switching and RSSI measurement via ADC. Use Value: SCTimer generates precise 125 kHz/13.56 MHz carrier waveforms; 164 GPIOs support multi-antenna matrix control and LED status indication. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC4357JET256 | Includes LCD controller and additional 32 kB SRAM; same dual-core, flash, and peripheral set otherwise. | Required for HMI-integrated designs (e.g., panel meters with TFT display); unnecessary overhead for headless gateways or motor drives. | Select LPC4357JET256 only if LCD interface and extra SRAM are needed - increases cost and power by ~8 %. |
| LPC4330JET256 | Same package and temperature grade but reduced flash (512 kB) and no Ethernet MAC; retains dual USB and C_CAN. | Suitable for USB-centric embedded controllers (e.g., USB-to-CAN bridges) where Ethernet is not required. | Choose LPC4330JET256 to reduce BOM cost by ~12 % when Ethernet connectivity is omitted from system architecture. |
Compared with LPC4357JET256, LPC4337JET256Y removes LCD support to lower cost and power while retaining full Ethernet/USB/CAN capability; versus LPC4330JET256, it adds Ethernet MAC and 512 kB flash - making it optimal for industrial gateways needing network edge intelligence without display.
Availability
LPC4337JET256Y is available at Aetrix Electronics and suitable for industrial automation, smart energy metering, and RFID reader applications requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for LPC4337JET256Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in ARM-based microcontrollers and edge processing.
The LPC43xx product line was engineered for deterministic real-time control in resource-constrained industrial systems - combining dual-core flexibility, rich analog/digital peripherals, and hardware-accelerated networking to replace discrete MCU + FPGA architectures.
FAQ
What is the maximum operating frequency of the LPC4337JET256Y Cortex-M4F core?
The LPC4337JET256Y Cortex-M4F core operates at up to 204 MHz, as confirmed in the NXP LPC435x/3x/2x/1x datasheet Rev. 5.4. This frequency is sustained across the full -40 °C to +105 °C temperature range with appropriate voltage regulation (3.3 V ±10 %). The LPC4337JET256Y achieves this performance using three on-chip PLLs, with the main PLL configured for 204 MHz output without requiring an external high-frequency crystal.
Does the LPC4337JET256Y include an LCD controller?
No, the LPC4337JET256Y does not include an LCD controller. According to Table 2 in the NXP datasheet, LCD support is explicitly marked "no" for all LPC433x variants, including LPC4337JET256Y. In contrast, LPC435x parts (e.g., LPC4357JET256) feature a full LCD controller supporting up to 1024 × 768 resolution. This omission reduces die size and power consumption, making LPC4337JET256Y ideal for headless industrial controllers.
What is the purpose of the dual-core architecture in the LPC4337JET256Y?
The dual-core architecture in the LPC4337JET256Y separates real-time deterministic tasks (Cortex-M4F) from peripheral management and protocol stacks (Cortex-M0). For example, the Cortex-M4F can run motor control algorithms while the Cortex-M0 handles USB device enumeration or Ethernet MAC interrupt servicing - eliminating priority inversion and ensuring sub-microsecond response to time-critical events. This is validated in NXP's LPC43xx reference designs for industrial gateways.
Which USB interfaces does the LPC4337JET256Y support, and how are they implemented?
The LPC4337JET256Y supports two independent USB 2.0 interfaces: USB0 includes an on-chip high-speed PHY and supports Host/Device/OTG modes with DMA; USB1 uses an ULPI interface to connect to an external high-speed PHY and supports Host/Device modes. Both interfaces are fully compliant with USB 2.0 specifications and include ROM-resident USB stack test software - enabling rapid development of certified USB peripherals without external transceivers for USB0.
How many GPIO pins does the LPC4337JET256Y provide, and what advanced I/O features are supported?
The LPC4337JET256Y provides 164 GPIO pins across 16 ports (P0–P9, PA–PF), each configurable via the System Configuration Unit (SCU) for up to eight alternate functions. Advanced features include DMA-capable GPIO registers on the AHB bus, eight dedicated GPIO interrupt sources, two GPIO group interrupt modules for pattern-matching wakeups, and individual power-down control for SRAM blocks - enabling ultra-low-power operation in battery-backed applications like smart meters.
LPC4337JET256Y Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 256-LBGA
- Series:
- LPC43xx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M4/M0
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 204MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, IrDA, Microwire, QEI, SD, SPI, SSI, SSP, UART/USART, USB, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, Motor Control PWM, POR, PWM, WDT
- Number of I/O:
- 164
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 16K x 8
- RAM Size:
- 136K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.2V ~ 3.6V
- Data Converters:
- A/D 8x10b; D/A 1x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC4337JET256Y FAQ
1.How can I place an order for LPC4337JET256Y through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC4337JET256Y on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC4337JET256Y reliable?
The price and inventory of LPC4337JET256Y are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC4337JET256Y is usually 5 days.
3.What payment methods are accepted for LPC4337JET256Y?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC4337JET256Y transactions.
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4.How is shipping managed for LPC4337JET256Y?
LPC4337JET256Y orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC4337JET256Y order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC4337JET256Y?
For technical support, including LPC4337JET256Y datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC4337JET256Y requirements.
6.How does Aetrix verify that LPC4337JET256Y is sourced from the original manufacturer or authorized distributors?
All LPC4337JET256Y products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC4337JET256Y meets industry standards.
7.What is the process for return or replacement of LPC4337JET256Y?
All LPC4337JET256Y units undergo pre-shipment inspection (PSI). If there is an issue with LPC4337JET256Y, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC4337JET256Y part is unused and in its original packaging.
Return procedure for LPC4337JET256Y:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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