NXP Semiconductors LPC43S37JET100E
- Part No.:
- LPC43S37JET100E
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 100-TFBGA
- Datasheet:
-
LPC43S37JET100E.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 100TFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:1,696
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC43S37JET100E from NXP Semiconductors is a dual-core ARM Cortex-M4F/M0 microcontroller for industrial and embedded control applications, featuring 1 MB flash (512 kB per bank), 136 kB SRAM, integrated AES encryption engine, dual USB 2.0 interfaces (one with on-chip HS PHY, one with ULPI), and 10/100T Ethernet MAC with IEEE 1588 support - deployed in motor control, e-metering, and RFID reader systems.
For engineers reviewing the LPC43S37JET100E datasheet, LPC43S37JET100E pinout, LPC43S37JET100E application, or LPC43S37JET100E equivalent, key selection considerations include its TFBGA100 package with 49 GPIOs, absence of LCD controller and QEI, single USB1 without on-chip HS PHY, and 4-channel ADC configuration - critical for footprint-constrained, security-aware, real-time industrial designs.
Technical Context
The LPC43S37JET100E integrates an ARM Cortex-M4F core (up to 204 MHz) with hardware FPU and MPU, paired with a fully independent Cortex-M0 coprocessor (also up to 204 MHz) for offloading real-time tasks. Its memory subsystem includes dual-bank flash with accelerator, 16 kB EEPROM, and segmented SRAM blocks - two of which support individual power-down.
Peripherals are routed via AHB multilayer matrix and GIMA crossbar, enabling flexible event-driven routing between timers (SCT, general-purpose), ADCs, and communication interfaces. The device supports secure boot via AES-128 engine with OTP key storage and ROM-based API, and features three PLLs - one dedicated to USB, one to audio, and one for CPU clock generation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: ARM Cortex-M4F @ 204 MHz + Cortex-M0 @ 204 MHz - enables asymmetric task partitioning with shared memory and inter-processor messaging. |
| Flash Memory | 1 MB total (512 kB Bank A + 512 kB Bank B) with flash accelerator - supports live firmware updates and secure dual-bank booting. |
| SRAM | 136 kB distributed across multiple AHB/local blocks - allows selective power-down of unused SRAM banks to reduce active power. |
| ADC | Two 10-bit ADCs, 400 kSamples/s, 4 input channels total - sufficient for sensor acquisition in e-metering and motor control feedback loops. |
| USB Interfaces | USB0: HS Host/Device/OTG with on-chip HS PHY; USB1: HS Host/Device with ULPI interface only - requires external PHY for full-speed operation on USB1. |
| Ethernet | 10/100T MAC with RMII/MII, DMA, and IEEE 1588-2008 v2 timestamping - enables precise time-synchronized industrial networking. |
| Security | AES-128 engine with DMA support and two 256-bit OTP banks - one for encrypted boot image decryption, one for general key storage. |
| Package | TFBGA100 (9 × 9 × 0.7 mm, SOT926-1) - compact footprint ideal for space-constrained industrial modules and metering PCBs. |
Pinout & Package
TFBGA100 package with 100-ball array (0.5 mm pitch), body size 9 mm × 9 mm × 0.7 mm, lead-free and RoHS-compliant. Pin functions validated per NXP LPC43S5x/S3x datasheet Rev. 1.3 (2020), Table 3 - specific to TFBGA100 column.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0_0 (G2) | GPIO / SSP1_MISO / ENET_RXD1 / I2S0_TX_WS | Multi-function digital I/O supporting Ethernet receive, SPI slave data input, and I2S word select - configurable via SCU registers for system-level signal routing. |
| P1_15 (K8) | GPIO / ENET_RXD0 / U2_TXD / T0_MAT1 | Combines Ethernet RX data line, USART2 transmit, and timer match output - enables synchronized packet handling and waveform generation on same pin. |
| P1_19 (K9) | ENET_TX_CLK / SSP1_SCK / CLKOUT / I2S0_RX_MCLK | Shared clock resource for Ethernet transmit timing, SPI serial clock, system clock output, and I2S master clock - simplifies clock tree design in multi-interface systems. |
| P2_3 (D8) | SGPIO12 / I2C1_SDA / U3_TXD / CTIN_1 | Supports I2C data, USART3 transmit, SCT capture input, and general-purpose I/O - facilitates mixed-signal sensor interfacing and event-triggered state transitions. |
| P2_5 (D10) | SGPIO14 / CTIN_2 / USB1_VBUS / ADCTRIG1 | Enables USB bus presence detection, ADC trigger synchronization, and SCT capture - critical for power-aware peripheral wake-up and sampled-data acquisition timing. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core asymmetric processing | Offloads deterministic real-time tasks (e.g., motor PWM, encoder counting) to Cortex-M0 while Cortex-M4 handles protocol stacks and UI - reduces software complexity and improves latency predictability. |
| Secure boot with AES-128 | Boot image decryption using keys stored in OTP memory prevents unauthorized firmware execution - essential for certified metering and industrial control deployments. |
| Configurable peripheral routing (GIMA) | Allows dynamic assignment of timer captures, ADC triggers, and interrupt sources across GPIO pins - eliminates fixed hardware dependencies and increases board layout flexibility. |
| Dual USB with distinct PHY options | USB0 includes integrated high-speed PHY for plug-and-play connectivity; USB1 uses ULPI for external PHY selection - balances cost, performance, and design reuse across product variants. |
| IEEE 1588-2008 v2 support | Hardware timestamping in Ethernet MAC enables sub-microsecond time synchronization across distributed nodes - required for coordinated motion control and precision grid monitoring. |
Applications
| Motor Control | e-Metering |
|---|---|
Use Scenario: Three-phase BLDC motor drive with current sensing, position feedback, and field-oriented control. IC Role / Device Role / Timing Role: Main controller executing FOC algorithm on Cortex-M4F; Cortex-M0 handles PWM generation, QEI decoding (via GPIO emulation), and ADC sampling triggers. Use Value: Dual-core architecture isolates timing-critical motor control loops from higher-layer communication stacks - ensuring jitter-free 20 kHz PWM and <1 µs interrupt latency. | Use Scenario: Smart electricity meter with tariff switching, tamper detection, and DLMS/COSEM protocol over PLC or RF. IC Role / Device Role / Timing Role: Secure host processor managing encrypted metering data, AES-protected firmware updates, and IEEE 1588-synchronized time-of-use billing. Use Value: On-chip AES engine and OTP key storage eliminate external crypto ICs; dual-bank flash enables fail-safe remote firmware upgrades without service interruption. |
| RFID Reader | Industrial Gateway |
Use Scenario: UHF RFID reader with ISO 18000-6C protocol stack, antenna switching, and tag inventory management. IC Role / Device Role / Timing Role: Baseband processor handling Manchester decoding, CRC verification, and anti-collision logic; USB0 provides HID-class interface to host PC. Use Value: High-speed USB OTG and 204 MHz Cortex-M4F enable real-time tag response parsing at >1000 tags/sec - exceeding EPCglobal Class 1 Gen 2 throughput requirements. | Use Scenario: Protocol gateway bridging Modbus RTU (RS-485) to Ethernet/IP or MQTT over TLS. IC Role / Device Role / Timing Role: Dual-core coordination: Cortex-M0 manages UART/SSP peripherals and watchdog supervision; Cortex-M4F runs TCP/IP stack, TLS handshake, and web server. Use Value: Segregated memory and independent reset domains prevent network stack crashes from disrupting fieldbus communication - meeting IEC 61131-3 reliability requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core ARM microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC4357JBD208 | 208-pin LQFP package; includes LCD controller and QEI; 142 GPIOs; same flash/SRAM/AES/USB/Ethernet specs. | Required for TFT display interfaces and quadrature encoder-based motion systems - not suitable for TFBGA100 footprint or LCD-free designs. | Select when display output or hardware QEI is mandatory; avoid if board area or thermal constraints favor TFBGA100. |
| LPC4337JBD144 | 144-pin LQFP package; no LCD or QEI; 83 GPIOs; identical core/peripheral set except missing USB1 HS PHY. | Matches LPC43S37JET100E feature set closely but lacks USB0's on-chip HS PHY - requires external PHY for full USB2.0 speed. | Prefer for cost-sensitive LQFP designs where USB0 speed is non-critical; verify USB1 PHY compatibility before migration. |
Compared with LPC43S37JET100E, LPC4357JBD208 adds LCD/QEI at the cost of larger footprint and higher pin count, while LPC4337JBD144 trades USB0 HS PHY for LQFP packaging - making LPC43S37JET100E the optimal choice for compact, USB2.0-capable, security-focused industrial modules.
Availability
LPC43S37JET100E is available at Aetrix Electronics and suitable for motor control, e-metering, and RFID reader applications requiring stable component supply, long-term industrial lifecycle support, and traceable sourcing from authorized NXP channels.
Supply support for LPC43S37JET100E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in ARM-based microcontrollers and edge processing.
The LPC43Sxx series was designed for high-integrity embedded applications demanding dual-core determinism, hardware-accelerated security, and rich peripheral integration - targeting industrial automation, smart energy, and secure gateways.
FAQ
What is the maximum operating frequency of the LPC43S37JET100E?
The LPC43S37JET100E operates at a maximum CPU frequency of 204 MHz for both the ARM Cortex-M4F and Cortex-M0 cores. This frequency is achieved using the on-chip PLLs fed by the internal 12 MHz RC oscillator or an external crystal (1–25 MHz). The M4F core includes a hardware floating-point unit and memory protection unit, while the M0 core maintains full code and tool compatibility with the M4F - enabling efficient asymmetric processing in real-time applications.
Does the LPC43S37JET100E include an LCD controller?
No, the LPC43S37JET100E does not include an LCD controller. According to Table 2 in the NXP LPC43S5x/S3x datasheet Rev. 1.3, the LCD feature is explicitly marked "no" for the LPC43S37JET100 variant. This omission distinguishes it from higher-pin-count variants like LPC43S57JET256 and LPC43S57JBD208, which support programmable display resolutions up to 1024×768. The LPC43S37JET100E retains all other major peripherals including Ethernet, dual USB, AES, and dual ADCs - optimized for compact, non-display industrial applications.
How many ADC channels does the LPC43S37JET100E support?
The LPC43S37JET100E supports four total ADC input channels - two 10-bit ADCs (ADC0 and ADC1), each with four dedicated input channels. As confirmed in Table 2 and Section 2.2 ("Analog peripherals") of the datasheet, this is half the eight-channel capability found in LPC43S5x variants. Each ADC achieves 400 kSamples/s with DMA support, and channel inputs are multiplexed across shared pins - allowing simultaneous sampling for current/voltage sensing in motor control or energy measurement applications.
What USB PHY configurations are supported on the LPC43S37JET100E?
The LPC43S37JET100E supports two USB 2.0 interfaces with distinct PHY implementations: USB0 integrates an on-chip high-speed PHY, enabling direct connection to USB connectors without external components; USB1 provides only a ULPI interface, requiring an external high-speed PHY chip (e.g., SMSC USB3343) for full-speed or high-speed operation. This configuration balances integration and flexibility - USB0 delivers plug-and-play functionality, while USB1 allows PHY selection based on EMI, cost, or legacy compatibility requirements in the final design.
Is the LPC43S37JET100E qualified for extended temperature operation?
Yes, the LPC43S37JET100E is rated for operation from −40 °C to +105 °C, as indicated by the "J" suffix in its part number per Table 1 of the NXP datasheet. This industrial temperature grade is validated across all specified electrical parameters, including flash programming, SRAM retention, USB signaling integrity, and Ethernet MAC timing - making it suitable for deployment in harsh environments such as outdoor metering enclosures, factory-floor controllers, and transportation infrastructure equipment.
LPC43S37JET100E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 100-TFBGA
- Series:
- LPC43xx
- Packaging:
- Bulk
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M4/M0
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 204MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, IrDA, Microwire, MMC/SD, SPI, SSI, SSP, UART/USART, USB, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, POR, WDT
- Number of I/O:
- 49
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 136K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.2V ~ 3.6V
- Data Converters:
- A/D 4x10b; D/A 1x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC43S37JET100E FAQ
1.How can I place an order for LPC43S37JET100E through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC43S37JET100E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC43S37JET100E reliable?
The price and inventory of LPC43S37JET100E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC43S37JET100E is usually 5 days.
3.What payment methods are accepted for LPC43S37JET100E?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC43S37JET100E transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC43S37JET100E?
LPC43S37JET100E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC43S37JET100E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC43S37JET100E?
For technical support, including LPC43S37JET100E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC43S37JET100E requirements.
6.How does Aetrix verify that LPC43S37JET100E is sourced from the original manufacturer or authorized distributors?
All LPC43S37JET100E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC43S37JET100E meets industry standards.
7.What is the process for return or replacement of LPC43S37JET100E?
All LPC43S37JET100E units undergo pre-shipment inspection (PSI). If there is an issue with LPC43S37JET100E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC43S37JET100E part is unused and in its original packaging.
Return procedure for LPC43S37JET100E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC43S37JET100E Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

