NXP Semiconductors LPC43S67JET100E

Overview

LPC43S67JET100E from NXP Semiconductors is a dual-core ARM Cortex-M4/M0 microcontroller for industrial and embedded control applications, featuring 1 MB flash, 154 kB SRAM, dual High-speed USB 2.0 interfaces (one with on-chip HS PHY, one with ULPI), 10/100T Ethernet MAC with IEEE 1588 support, and AES encryption engine. It operates at up to 204 MHz and targets secure, real-time, connectivity-rich systems such as e-metering gateways and industrial IoT edge nodes.

For engineers reviewing the LPC43S67JET100E datasheet, LPC43S67JET100E pinout, LPC43S67JET100E application, or LPC43S67JET100E equivalent, key selection considerations include its TFBGA100 package (9 × 9 mm), absence of integrated LCD controller, 4-channel ADC support (vs. 8 in larger variants), and 49 GPIO pins - critical for space-constrained, cost-optimized designs requiring USB/Ethernet coexistence without display output.

Technical Context

The LPC43S67JET100E integrates an ARM Cortex-M4 core (r0p1) with hardware FPU and MPU, paired with an application-oriented ARM Cortex-M0 coprocessor (r0p0) and a dedicated Cortex-M0 subsystem managing SGPIO/SPI peripherals via a core-to-core bridge. Its memory architecture includes dual-bank 512 kB flash per bank, 16 kB EEPROM, and segmented SRAM blocks - two of which support independent power-down.

Peripherals are distributed across three AHB multilayer matrices: main (Cortex-M4), subsystem (Cortex-M0), and peripheral bridges. The device supports IEEE 1588-2008 v2 time stamping via Ethernet MAC, uses three independent PLLs (CPU, USB, audio), and implements AES decryption/encryption with DMA and ROM-based API access - all validated for boot image security.

Key Specifications

Pinout & Package

Package: TFBGA100 (9 × 9 × 0.7 mm, 100-ball fine-pitch ball grid array). Pin assignments follow NXP's standardized LPC43S6x TFBGA100 layout (SOT926-1), with multiplexed functions per pin including GPIO, Ethernet, USB, SPI, I²C, I²S, ADC, and timer I/O. Ball A1 is index corner; top-side view orientation matches standard BGA conventions.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core ARM microcontroller applications.

Compared with LPC43S57JET100E and LPC4357JET100E, the LPC43S67JET100E uniquely balances security (AES + OTP), compact packaging (TFBGA100), and dual high-speed connectivity - making it optimal for certified metering and secure edge nodes where LCD is omitted and crypto is mandatory.

Availability

LPC43S67JET100E is available at Aetrix Electronics and suitable for smart metering gateways, industrial Ethernet I/O modules, and secure RFID reader controllers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for LPC43S67JET100E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in ARM-based microcontrollers and trusted execution environments.

The LPC43S6x product line was designed for high-performance, security-critical embedded applications demanding dual-core real-time processing, hardware-accelerated cryptography, and multi-protocol wired connectivity - particularly in utility metering, industrial control, and secure peripherals.

FAQ

What is the maximum operating frequency of the LPC43S67JET100E?

The LPC43S67JET100E operates at a maximum CPU frequency of 204 MHz for both its ARM Cortex-M4 and ARM Cortex-M0 cores. This performance level is achieved using internal PLLs that allow full-speed operation without requiring a high-frequency external crystal oscillator, supporting deterministic real-time response in demanding industrial applications.

Does the LPC43S67JET100E include an LCD controller?

No, the LPC43S67JET100E does not include an LCD controller. As confirmed in Table 2 of the official datasheet, the "LCD" column for LPC43S67JET100 is marked "no", distinguishing it from larger-package variants like LPC43S67JBD208 and LPC43S67JET256. This omission reduces die size and cost while maintaining full USB/Ethernet functionality in the TFBGA100 package.

How many ADC channels does the LPC43S67JET100E support?

The LPC43S67JET100E supports four total ADC input channels - two 10-bit ADCs (ADC0 and ADC1), each with four dedicated input channels. This is explicitly stated in Table 2 ("ADC channels: 4") and aligns with the device's positioning as a compact, cost-optimized variant within the LPC43S6x family, targeting applications where full 8-channel capability is unnecessary.

What security features are integrated into the LPC43S67JET100E?

The LPC43S67JET100E integrates a hardware AES engine with DMA support, programmable via a ROM-based API, and two 256-bit OTP memory banks for encrypted boot key storage - one bank stores an encrypted key used to decode the boot image. These features enable secure boot verification and runtime data encryption, satisfying requirements for certified e-metering and payment-terminal applications.

Which package type is used for the LPC43S67JET100E?

The LPC43S67JET100E uses the TFBGA100 package (SOT926-1): a plastic thin fine-pitch ball grid array with 100 balls, 9 mm × 9 mm body size, and 0.7 mm height. This compact, surface-mount package is optimized for space-constrained industrial modules and supports automated assembly with standard reflow profiles.