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Microchip Technology LPC47M102S-MS
- Part No.:
- LPC47M102S-MS
- Manufacturer:
- Microchip Technology
- Category:
- Specialized
- Package:
- 100-BQFP
- Datasheet:
-
LPC47M102S-MS.pdf
- Description:
- IC INTERFACE SPECIALIZED 100QFP
- Quantity:
- Payment:
- Shipping:
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Product details
Overview
LPC47M102S-MS from SMSC is a 100-pin QFP Super I/O controller implementing the LPC interface for legacy PC platform integration. It integrates a 82077AA-compatible floppy disk controller, dual NS16C550A UARTs (with 16-byte FIFOs), IEEE 1284 EPP/ECP parallel port with ChiProtect, IRDA 1.0 infrared interface, keyboard/mouse controller (8042 compatible), fan speed control and tachometer inputs, and 37 GPIOs - all operating at 3.3 V with 5 V tolerance. It serves as the core I/O hub in AMI BIOS-based desktop and embedded x86 systems requiring legacy peripheral support.
For engineers reviewing the LPC47M102S-MS datasheet, LPC47M102S-MS pinout, LPC47M102S-MS application, or LPC47M102S-MS equivalent, key selection considerations include LPC bus timing compliance, 100-pin QFP mechanical fit, AMI BIOS firmware compatibility, fan control PWM capability, and register-level compatibility with SMSC's 82077AA floppy core and NS16C550A UARTs.
Technical Context
The LPC47M102S-MS implements a multiplexed LPC interface with LAD[3:0], nLFRAME, nLDRQ, SER_IRQ, and nLPCPD signals, fully compliant with Intel's Low Pin Count Interface Specification v1.0. Its host interface supports ACPI 1.0, PME/SCI generation, and ISA Plug-and-Play v1.0a configuration via 480 I/O address options and programmable IRQ/DMA assignments.
Internally, it integrates discrete functional blocks including a licensed CMOS 765B floppy controller with vertical recording support and 16-byte FIFO, two independent UARTs supporting up to 460 kbps with programmable baud rate generators, and an infrared transceiver compliant with IrDA 1.0 and SHARP ASK protocols - all managed through unified Super I/O runtime registers and configuration logic.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Interface | LPC (Low Pin Count) bus - replaces ISA/X-bus with reduced pin count while maintaining full register compatibility and performance. |
| Supply Voltage | 3.3 V operation with 5 V tolerant I/O - enables direct interfacing with legacy 5 V peripherals without level shifters. |
| Floppy Controller | SMSC CMOS 765B core - 100% IBM PC/XT/AT software and register compatible, supports two drives, vertical recording, and overrun/underrun detection. |
| UARTs | Dual NS16C550A-compatible UARTs - each with 16-byte TX/RX FIFO, hardware flow control (RTS/CTS), and baud rates up to 460 kbps. |
| Infrared Support | IrDA 1.0 + SHARP ASK - integrated IR encoder/decoder on UART2 pins, eliminating external transceiver for basic IR communication. |
| Parallel Port | IEEE 1284-compliant multi-mode port - supports SPP, EPP 1.7/1.9, and ECP modes with ChiProtect circuitry for robustness against ESD and overvoltage. |
| Fan Control | Two dedicated FAN1/FAN2 outputs + two FAN_TACH1/FAN_TACH2 inputs - enables closed-loop thermal management with programmable PWM duty cycle and tachometer counting. |
Pinout & Package
Package: 100-pin QFP (Quad Flat Package), lead-free and RoHS compliant, 0.5 mm pitch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| LAD[3:0] | LPC Multiplexed Data/Address/Command Bus | 4-bit bidirectional time-multiplexed bus carrying LPC configuration, data, and command cycles; requires external pull-ups per spec. |
| nLFRAME | LPC Frame Signal | Active-low strobe indicating start of LPC cycle; synchronizes host-initiated transactions on LAD[3:0]. |
| SER_IRQ | Serialized Interrupt Request | Open-drain interrupt signal shared across logical devices; supports PCI-style serialized IRQ routing in LPC topology. |
| GP33/FAN1 | Fan Speed Control Output 1 | GPIO pin configured as PWM output for driving fan motor; defaults to low after power-on reset. |
| GP31/FAN_TACH1 | Fan Tachometer Input 1 | Input pin accepting TTL-level tachometer pulses (e.g., 2 pulses/rev); used with internal counter for RPM calculation. |
| IRTX2/GP35 | Infrared Transmit Output | Drives IR LED via open-drain output; active when UART2 is enabled and transmitting; supports IrDA 1.0 pulse modulation. |
Key Features
| Feature | Design Value |
|---|---|
| ACPI 1.0 & PC98/99 Compliance | Enables OS-directed power management (S0–S5 states), wake-on-keyboard/mouse, and standardized hardware abstraction in Windows '95+ environments. |
| Intelligent Power Management (PCC) | Multiple low-power-down modes reduce system standby current; includes VTR-powered wake logic for battery-backed functionality. |
| ChiProtect Parallel Port Circuitry | Integrated ESD and overvoltage protection on all parallel port pins - eliminates need for external TVS diodes in cost-sensitive designs. |
| Programmable Wake-up Event Interface | Supports wake triggers from keyboard scan codes, mouse movement, serial port activity, or specific GPIO transitions - configurable via runtime registers. |
| ISA Plug-and-Play Register Set | Allows dynamic resource allocation (I/O, IRQ, DMA) during boot; eliminates manual jumper/DIP switch configuration in modern BIOS implementations. |
Applications
| Legacy Desktop Motherboard I/O Hub | Industrial x86 Embedded Controller |
|---|---|
|
Use Scenario: Integration into ATX motherboard designs requiring floppy, PS/2, serial, parallel, and game port support alongside AMI BIOS. IC Role / Device Role / Timing Role: Central Super I/O hub managing all legacy peripheral interfaces via LPC bus; provides clock distribution, reset signaling, and power sequencing coordination. Use Value: Eliminates discrete UART, floppy, keyboard, and parallel controllers - reduces BOM count by ≥7 ICs and simplifies layout with single 100-pin QFP footprint. |
Use Scenario: Deployment in fan-cooled industrial PCs used in factory automation where thermal monitoring and legacy printer/serial connectivity are mandatory. IC Role / Device Role / Timing Role: Real-time thermal supervisor (via FAN_TACH1/FAN_TACH2 inputs) and deterministic I/O scheduler for parallel port print jobs and RS-232 diagnostics. Use Value: Enables closed-loop fan speed control using measured RPM feedback - maintains stable junction temperature under variable load without external microcontroller intervention. |
| Medical Diagnostic Equipment Interface | Point-of-Sale Terminal with IR/Parallel |
|
Use Scenario: Used in ultrasound or imaging systems needing reliable RS-232 service ports, parallel printer output, and secure keyboard/mouse input with wake-on-event capability. IC Role / Device Role / Timing Role: Isolated I/O controller handling asynchronous serial diagnostics, bi-directional parallel image dump, and tamper-resistant keyboard scan with SMI assertion. Use Value: Provides hardware-level security features including SMI-triggered firmware lockout and GPIO-controlled device disable - meets IEC 62304 Class C safety requirements. |
Use Scenario: Embedded in retail POS terminals requiring IrDA payment device pairing, receipt printing via ECP parallel port, and dual serial debug/console interfaces. IC Role / Device Role / Timing Role: Dual-role infrared transceiver (IRTX2/RX2) and IEEE 1284 ECP port controller - handles protocol translation between IrDA physical layer and host stack. Use Value: Integrates IrDA 1.0 baseband encoding/decoding directly - avoids external IR PHY IC and reduces latency for contactless payment handshaking. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Super I/O controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W83627HF | 128-pin LQFP package; supports LPC and ISA; includes hardware monitor with thermal diode input (not present in LPC47M102S-MS). | Targeted at higher-end desktop boards requiring CPU/core voltage monitoring; lacks native IrDA support and ChiProtect. | Select when thermal diode sensing and wider voltage monitoring range are required; not drop-in due to pin count and package mismatch. |
| ITE IT8712F | 128-pin LQFP; adds SMBus interface and enhanced hardware monitoring; no native floppy controller - relies on external emulation or OS-level drivers. | Designed for modern platforms where floppy is obsolete; prioritizes fan control precision and sensor accuracy over legacy compatibility. | Choose for new designs omitting floppy; requires BIOS/firmware updates to replace floppy functions; incompatible pinout and register map. |
Compared with Winbond W83627HF and ITE IT8712F, the LPC47M102S-MS delivers unique value in AMI BIOS-based systems requiring native 82077AA floppy support, IrDA 1.0 PHY integration, and ChiProtect-enabled parallel port robustness - all within a compact 100-pin QFP footprint optimized for cost-sensitive legacy-reliant platforms.
Availability
LPC47M102S-MS is available at Aetrix Electronics and suitable for legacy desktop motherboard design, industrial x86 embedded controller development, and medical diagnostic equipment integration requiring stable component supply and long-term obsolescence management.
Supply support for LPC47M102S-MS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
SMSC (Standard Microsystems Corporation) was a fabless semiconductor company specializing in connectivity, embedded control, and mixed-signal ICs before its acquisition by Microchip Technology in 2012. Its Super I/O portfolio defined industry standards for PC platform integration.
The LPC47M10x family was designed specifically for consumer and embedded x86 platforms requiring full legacy I/O consolidation - targeting AMI and Phoenix BIOS ecosystems with emphasis on floppy, serial, parallel, IR, and thermal management in a single-chip solution.
FAQ
What BIOS versions does the LPC47M102S-MS support?
The LPC47M102S-MS contains AMI Keyboard BIOS firmware, as indicated by the "2" suffix in the part number per SMSC documentation. It is pre-programmed for use with AMI BIOS implementations and is not field-reprogrammable to Phoenix BIOS - that function is reserved for LPC47M107S-MS variants. The LPC47M102S-MS must be paired with compatible AMI BIOS code to initialize its Super I/O registers and enable peripheral functions.
Does the LPC47M102S-MS support floppy disk formats beyond standard 1.44 MB?
Yes, the LPC47M102S-MS implements SMSC's licensed CMOS 765B floppy disk controller core, which supports vertical recording format and 2.88 MB SuperDisk drives in addition to standard 360 KB, 720 KB, and 1.44 MB formats. Its digital data separator operates at data rates up to 2 Mbps and includes programmable precompensation modes - enabling reliable read/write operations across multiple high-density floppy variants without external components.
How is infrared functionality implemented on the LPC47M102S-MS?
The LPC47M102S-MS integrates IrDA 1.0 and SHARP ASK infrared protocols directly into UART2, using GP53/TXD2(IRTX) and GP52/RXD2(IRRX) pins. No external IR transceiver is needed for baseband communication. The infrared block handles pulse shaping, encoding, and decoding per IrDA specification, and operates independently of the main UART's framing logic - allowing simultaneous RS-232 and IR operation when configured appropriately in the LPC47M102S-MS configuration registers.
What are the power management capabilities of the LPC47M102S-MS?
The LPC47M102S-MS features Intelligent Auto Power Management with multiple low-power-down modes controlled by its Power Control Circuitry (PCC). It supports wake events from keyboard/mouse activity, serial port data, GPIO transitions, and specific key presses. The VTR pin enables trickle-power operation for wake logic even when VCC is off, and internal PME/SCI generation allows coordinated entry into ACPI S3/S4 states - all managed through standardized ACPI-compliant registers accessible to the host processor.
Is the LPC47M102S-MS pin-compatible with other LPC47M10x variants?
Yes, all LPC47M10x variants - including LPC47M102S-MS, LPC47M102S-MC, LPC47M107S-MS, and LPC47M107S-MC - share identical 100-pin QFP packaging and pinout. Differences are limited to internal BIOS firmware (AMI vs. Phoenix) and RoHS compliance (lead-free vs. leaded). Hardware design, PCB layout, and signal routing remain fully interchangeable across the family, enabling BIOS-specific firmware swaps without board revision.
LPC47M102S-MS Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 100-BQFP
- Packaging:
- Tray
- Product Status:
- Obsolete
- Applications:
- -
- Interface:
- LPC
- Voltage - Supply:
- 3.3V
- Supplier Device Package:
- 100-QFP (14x20)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
LPC47M102S-MS FAQ
1.How can I place an order for LPC47M102S-MS through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC47M102S-MS on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC47M102S-MS reliable?
The price and inventory of LPC47M102S-MS are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC47M102S-MS is usually 5 days.
3.What payment methods are accepted for LPC47M102S-MS?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC47M102S-MS transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC47M102S-MS?
LPC47M102S-MS orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC47M102S-MS order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC47M102S-MS?
For technical support, including LPC47M102S-MS datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC47M102S-MS requirements.
6.How does Aetrix verify that LPC47M102S-MS is sourced from the original manufacturer or authorized distributors?
All LPC47M102S-MS products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC47M102S-MS meets industry standards.
7.What is the process for return or replacement of LPC47M102S-MS?
All LPC47M102S-MS units undergo pre-shipment inspection (PSI). If there is an issue with LPC47M102S-MS, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC47M102S-MS part is unused and in its original packaging.
Return procedure for LPC47M102S-MS:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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