Microchip Technology LPC47M107S-MS
- Part No.:
- LPC47M107S-MS
- Manufacturer:
- Microchip Technology
- Category:
- Specialized
- Package:
- 100-BQFP
- Datasheet:
-
LPC47M107S-MS.pdf
- Description:
- IC INTERFACE SPECIALIZED 100QFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LPC47M107S-MS from SMSC is a 100-pin QFP, RoHS-compliant Super I/O controller supporting LPC interface, ACPI 1.0, PC98/PC99 compliance, and Phoenix 42i Keyboard BIOS. It integrates dual NS16C550A-compatible UARTs (16-byte FIFO, up to 460 kbps), 2.88 MB floppy disk controller (CMOS 765B core), and fan speed/tachometer control for thermal management in legacy PC motherboards.
For engineers reviewing the LPC47M107S-MS datasheet, LPC47M107S-MS pinout, LPC47M107S-MS application, or LPC47M107S-MS equivalent, key selection criteria include LPC bus compatibility, integrated keyboard/mouse controller (8042 software compatible), IEEE 1284 EPP/ECP parallel port support, IrDA 1.0 infrared interface, and Phoenix BIOS firmware binding.
Technical Context
The LPC47M107S-MS implements a multiplexed LPC interface with SER_IRQ serial interrupt support and PME signaling for ACPI power management. Its host interface replaces ISA/X-bus with 4-bit LAD[3:0] command/address/data bus, nLFRAME framing, and nLDRQ DMA request-enabling full register-level compatibility with Windows '95 Plug-and-Play.
Internally, it combines discrete functional blocks: SMSC's licensed CMOS 765B floppy controller with vertical recording support and 16-byte FIFO; dual UARTs with independent baud rate generators; multi-mode parallel port with ChiProtect circuitry; and MPU-401 MIDI UART with dedicated MIDI_IN/MIDI_OUT pins-all mapped via logical device configuration registers at 480 I/O address options.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| LPC Interface | Multiplexed 4-bit LAD[3:0], nLFRAME, nLDRQ, SER_IRQ - replaces ISA bus with reduced pin count while maintaining full register compatibility. |
| Floppy Controller | SMSC CMOS 765B core, 100% IBM PC/XT/AT compatible, supports two drives, vertical recording, 16-byte FIFO, and overrun/underrun detection. |
| UARTs | Two NS16C550A-compatible ports, each with 16-byte TX/RX FIFO, programmable baud up to 460 kbps, and modem control signals. |
| Parallel Port | IEEE 1284-compliant multi-mode: Standard, EPP 1.7/1.9, and ECP - includes ChiProtect for surge immunity and 14mA drive capability. |
| Infrared Interface | IrDA 1.0 and SHARP ASK IR compliant, with dedicated IRTX2/IRRX2 pins and configurable protocol selection. |
| Fan Control | Two PWM fan speed outputs (FAN1/FAN2) and two tachometer inputs (FAN_TACH1/FAN_TACH2) for closed-loop thermal regulation. |
| BIOS Binding | Phoenix 42i Keyboard BIOS embedded - determines default configuration, keyboard scan logic, and wake-on-key behavior. |
Pinout & Package
Package: 100-pin lead-free RoHS-compliant QFP (Quad Flat Package), 0.5 mm pitch, body size 14 × 14 mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| LAD[3:0] | LPC multiplexed data/address/command bus | 4-bit bidirectional bus carrying all LPC transactions; requires external pull-ups per specification. |
| nLFRAME | LPC frame signal | Active-low strobe indicating start of LPC cycle; synchronizes command decoding on host side. |
| SER_IRQ | Serialized interrupt output | Open-drain IRQ line shared across logical devices; supports PCI-style serialized interrupt routing. |
| FAN1 / GP33 | Fan speed control output | 12 mA sink/open-drain PWM output for driving fan cathode; defaults low after POR. |
| FAN_TACH1 / GP31 | Fan tachometer input | Schmitt-trigger input accepting TTL-level pulses from fan tach sensor; clock source selectable (32 kHz or internal). |
| IRTX2 / GP35 | Infrared transmit output | Push-pull output for IrDA 1.0 or SHARP ASK IR modulation; enabled only after Serial Port 2 activation. |
| GP25 / MIDI_IN | MIDI data input | GPIO configured as dedicated MIDI UART receive pin; supports MPU-401 protocol timing and framing. |
| nSTROBE | Parallel port strobe output | 14 mA push-pull active-low signal initiating data transfer to printer; part of IEEE 1284 ECP handshake. |
Key Features
| Feature | Design Value |
|---|---|
| ACPI 1.0 & PC98/99 Compliance | Enables OS-directed power management including SMI, PME, and wake-on-event (keyboard, mouse, fan, timer) in Windows '95 and later. |
| Integrated Floppy Controller | Eliminates need for external 765B-compatible chip; supports 2.88 MB format, vertical recording, and automatic error recovery. |
| Dual Full-Function UARTs | Each provides 16-byte FIFO, hardware flow control (RTS/CTS), and independent baud rate generation - reduces CPU overhead in serial communication. |
| ChiProtect Parallel Port | On-die transient voltage suppression protects against ESD and inductive kickback during hot-plug or cable disconnect events. |
| Phoenix 42i Keyboard BIOS | Pre-programmed firmware enables plug-and-play keyboard/mouse initialization, A20 gate control, and fast Gate-A20/KRESET outputs. |
| Intelligent Power Management | Multiple low-power-down modes, PCC circuitry, and VTR-powered LED/fan logic allow operation under trickle power (3.3 V standby). |
Applications
| Legacy Desktop Motherboard | Industrial Embedded PC |
|---|---|
Use Scenario: Mainboard I/O hub for ATX form-factor desktops requiring floppy, serial, parallel, and PS/2 interfaces. IC Role / Device Role / Timing Role: Central Super I/O controller managing LPC-to-legacy peripheral bridging, BIOS-integrated keyboard scanning, and system-level power sequencing. Use Value: Reduces BOM count by integrating 765B floppy controller, dual UARTs, ECP parallel port, and fan monitoring - eliminating 4–5 discrete ICs. | Use Scenario: Fan-cooled industrial control panel with RS-232 diagnostics, parallel printer interface, and thermal event logging. IC Role / Device Role / Timing Role: System monitor and interface aggregator providing real-time fan RPM feedback, UART-based firmware updates, and EPP-mode data capture. Use Value: Enables closed-loop thermal control using FAN_TACH1/FAN_TACH2 inputs and FAN1/FAN2 PWM outputs - no external tach conditioning required. |
| Medical Diagnostic Equipment | Point-of-Sale Terminal |
Use Scenario: Ultrasound or imaging workstation requiring reliable floppy boot media, infrared remote control, and MIDI audio alerts. IC Role / Device Role / Timing Role: Multi-protocol I/O processor handling IrDA 1.0 remote commands, MPU-401 MIDI tone generation, and secure floppy boot verification. Use Value: Integrates IrDA and MIDI functions on dedicated pins (IRTX2/IRRX2, GP25/GP26) - avoids signal crosstalk and timing conflicts in noise-sensitive analog environments. | Use Scenario: Retail terminal with receipt printer, barcode scanner (RS-232), and customer display (parallel port). IC Role / Device Role / Timing Role: Peripheral coordinator managing concurrent ECP parallel print jobs, UART-based scanner polling, and GPIO-driven status LEDs. Use Value: ChiProtect circuitry prevents ESD damage from frequent cable insertion/removal; GP60/GP61 LED outputs powered by VTR enable status indication during standby. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Super I/O controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC47M107S-MC | Same die, leaded package (non-RoHS), AMI BIOS not preloaded - requires external BIOS programming. | Used in legacy AMI-based designs where RoHS compliance is not mandated and reflow soldering is avoided. | Select LPC47M107S-MC only if leaded assembly process is required and Phoenix BIOS functionality is unnecessary. |
| Winbond W83977EF-AW | 128-pin QFP, supports LPC and ISA, includes hardware watchdog and temperature sensor - no built-in Phoenix BIOS. | Targeted at newer embedded platforms needing thermal monitoring and fail-safe reset, not legacy Phoenix BIOS dependency. | Choose W83977EF-AW when extended diagnostics, watchdog, or on-die thermal sensing are required - not for drop-in Phoenix BIOS replacement. |
Compared with LPC47M107S-MS, LPC47M107S-MC lacks RoHS compliance and Phoenix BIOS, limiting use in modern production; W83977EF-AW adds watchdog and thermal sensing but omits Phoenix firmware binding and requires PCB redesign due to 128-pin footprint.
Availability
LPC47M107S-MS is available at Aetrix Electronics and suitable for legacy desktop motherboard design, industrial embedded PC integration, and medical diagnostic equipment requiring stable component supply and long-term obsolescence management.
Supply support for LPC47M107S-MS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
SMSC (Standard Microsystems Corporation) was a fabless semiconductor company specializing in connectivity, embedded control, and mixed-signal ICs before acquisition by Microchip Technology in 2012.
The LPC47M10x family was designed specifically for cost-sensitive consumer PC platforms requiring integrated legacy I/O - delivering ISA replacement functionality via LPC while preserving Windows '95 Plug-and-Play and ACPI 1.0 compliance.
FAQ
What BIOS firmware is embedded in the LPC47M107S-MS?
The LPC47M107S-MS contains Phoenix 42i Keyboard BIOS firmware pre-programmed at manufacture. This determines default keyboard scan logic, A20 gate behavior, and wake-on-specific-key functionality. Unlike AMI-based variants (e.g., LPC47M102S-MS), it does not support field reprogramming of BIOS core - configuration is done via logical device registers only.
Does the LPC47M107S-MS support both EPP and ECP parallel port modes?
Yes, the LPC47M107S-MS supports IEEE 1284-compliant Enhanced Parallel Port (EPP) versions 1.7 and 1.9, as well as Enhanced Capabilities Port (ECP) mode. The parallel port uses ChiProtect circuitry for ESD resilience and provides 14 mA drive strength on nSTROBE, nACK, and BUSY lines - enabling direct connection to standard printers without external buffers.
How many fan control channels does the LPC47M107S-MS provide, and what is their electrical specification?
The LPC47M107S-MS provides two independent fan control channels: FAN1 (GP33) and FAN2 (GP32), each implemented as 12 mA sink/open-drain outputs capable of PWM duty-cycle modulation. Both pins default low after power-on reset and support closed-loop speed regulation using corresponding tachometer inputs FAN_TACH1 (GP31) and FAN_TACH2 (GP30).
Can the LPC47M107S-MS operate without a 32.768 kHz clock input?
Yes, the LPC47M107S-MS can operate without an external 32.768 kHz clock. When CLKI32 is grounded, the internal oscillator is used for fan tachometer timing, LED control, and wake-on-key logic - provided bit 7 of configuration register 0xF0 (Logical Device A) is set to '1' to select internal clock source.
What is the function of the VTR pin on the LPC47M107S-MS, and how is it used in power management?
The VTR pin supplies trickle power (3.3 V) to maintain LED control (GP60/GP61), fan monitoring, and wake-event logic when main VCC is off. It enables low-power standby operation - for example, allowing fan tachometer pulses to trigger wake-up even during S3 suspend. If wake functionality is unused, VTR may be tied to VCC; otherwise, it must be driven independently.
LPC47M107S-MS Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 100-BQFP
- Packaging:
- Tray
- Product Status:
- Obsolete
- Applications:
- -
- Interface:
- LPC
- Voltage - Supply:
- 3.3V
- Supplier Device Package:
- 100-QFP (14x20)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
LPC47M107S-MS FAQ
1.How can I place an order for LPC47M107S-MS through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC47M107S-MS on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC47M107S-MS reliable?
The price and inventory of LPC47M107S-MS are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC47M107S-MS is usually 5 days.
3.What payment methods are accepted for LPC47M107S-MS?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC47M107S-MS transactions.
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4.How is shipping managed for LPC47M107S-MS?
LPC47M107S-MS orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC47M107S-MS order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC47M107S-MS?
For technical support, including LPC47M107S-MS datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC47M107S-MS requirements.
6.How does Aetrix verify that LPC47M107S-MS is sourced from the original manufacturer or authorized distributors?
All LPC47M107S-MS products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC47M107S-MS meets industry standards.
7.What is the process for return or replacement of LPC47M107S-MS?
All LPC47M107S-MS units undergo pre-shipment inspection (PSI). If there is an issue with LPC47M107S-MS, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC47M107S-MS part is unused and in its original packaging.
Return procedure for LPC47M107S-MS:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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