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Microchip Technology LPC47M182-NW
- Part No.:
- LPC47M182-NW
- Manufacturer:
- Microchip Technology
- Category:
- Specialized
- Package:
- 128-BQFP
- Datasheet:
-
LPC47M182-NW.pdf
- Description:
- IC INTERFACE SPECIALIZED 128QFP
- Quantity:
- Payment:
- Shipping:
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Product details
Overview
LPC47M182-NW from Microchip Technology is a 3.3V (5V tolerant), PC99a/PC2001-compliant Advanced I/O Controller implementing the Low Pin Count (LPC) interface in a 128-pin QFP package. It integrates legacy I/O functions-including dual 16C550A UARTs, a CMOS 765B floppy controller, multi-mode parallel port with ChiProtect, infrared interface, and keyboard/mouse controller-alongside motherboard GLUE logic for power sequencing, 5V reference generation, and resume reset signaling. It serves as a space-saving, cost-optimized I/O hub for desktop PC motherboards requiring ACPI 1.0b/2.0 compliance and ISA Plug-and-Play register compatibility.
For engineers reviewing the LPC47M182-NW datasheet, LPC47M182-NW pinout, LPC47M182-NW application, or LPC47M182-NW equivalent, key selection considerations include its 128-pin QFP RoHS-compliant footprint, LPC bus timing support, integrated PCC power control circuitry with wake-up event handling, and register-level compatibility with Microchip's 82077AA floppy core and 8042 keyboard controller.
Technical Context
The LPC47M182-NW implements a unified LPC interface supporting multiplexed command/address/data cycles and Serial IRQ signaling compatible with PCI systems. Its internal architecture includes an on-chip configuration register set enabling dynamic reassignment of up to 480 I/O addresses, 15 IRQs, and three DMA channels across logical devices.
It embeds discrete functional blocks: a true CMOS 765B floppy controller with 16-byte FIFO and vertical recording support; two high-speed UARTs with 16-byte FIFOs and IrDA 1.0–compliant infrared port; IEEE 1284–compliant EPP/ECP parallel port with ChiProtect; and a dedicated 8-bit 8042-compatible keyboard/mouse microcontroller with 2 kB ROM and 256 B RAM.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 3.3 V nominal, 5 V tolerant - enables direct interfacing with legacy 5 V peripherals without level-shifting circuitry. |
| Interface Standard | LPC bus compliant - replaces ISA bus with reduced pin count while maintaining full software compatibility via Serial IRQ and configuration registers. |
| Floppy Controller Core | CMOS 765B licensed core - delivers 100% IBM PC/XT/AT compatibility, including overrun/underrun detection and vertical format support. |
| UART Capability | Dual 16C550A-compatible ports with 16-byte FIFOs - supports up to 460 kbps baud rate and modem control signals for legacy serial device integration. |
| Parallel Port Mode | Multi-mode (SPP/EPP/ECP) with ChiProtect - provides IEEE 1284 compliance and robust electrostatic protection for front-panel or printer connections. |
| Power Management | ACPI 1.0b/2.0 and PC99a/PC2001 compliant - enables OS-directed power states, PME signaling, and hardware-controlled S3/S5 sleep/wake transitions. |
| Package | 128-pin QFP, 14 × 20 × 2.7 mm body, 3.2 mm footprint - RoHS-compliant surface-mount package optimized for desktop motherboard layout density. |
Pinout & Package
128-pin QFP (NW package), RoHS-compliant, 3.2 mm footprint, with lead pitch of 0.50 mm and coplanarity ≤ 0.08 mm. Body dimensions: 20.00 mm × 14.00 mm × 2.7 mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| LAD[3:0] | LPC Address/Data Bus | Multiplexed 4-bit bidirectional bus carrying LPC commands, addresses, and data - reduces pin count vs. ISA while preserving functional throughput. |
| nLFRAME | LPC Frame Signal | Indicates start/end of LPC transaction cycle - synchronizes host-to-device communication timing on shared bus. |
| nLDRQ | LPC DMA Request | Asserted by LPC47M182-NW to request DMA service from host - enables zero-CPU-overhead data transfers for floppy, UART, or parallel operations. |
| SER_IRQ | Serialized Interrupt Request | Single-wire interrupt channel supporting IRQ1–IRQ15 encoding - eliminates dedicated IRQ lines and simplifies routing on dense PCBs. |
| GP10–GP15 | General Purpose I/O | 13 configurable GPIO pins - provide system-level flexibility for status monitoring, control signaling, or board-specific glue logic implementation. |
| FAN_TACH1*, FAN_TACH2* | Fan Tachometer Inputs | Dedicated pulse-counting inputs for RPM monitoring of cooling fans - supports thermal management without external counters or timers. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated Motherboard GLUE Logic | Replaces discrete logic for nRSMRST, Power OK, 5V/5V_STBY references, IDE/PCI reset buffering, and VGA DDC voltage translation - reduces BOM count and board area. |
| Enhanced Digital Data Separator | On-chip analog front-end for floppy read/write with programmable precompensation - eliminates external filter components and improves signal integrity at 2 Mbps data rate. |
| SMBus Isolation Circuitry | Hardware isolation between main power well and resume power well - prevents leakage current during S5 state and ensures reliable wake-from-suspend behavior. |
| ChiProtect™ Parallel Port Protection | Integrated ESD and overvoltage protection on all parallel port pins - meets IEC 61000-4-2 Level 4 (±15 kV air, ±8 kV contact) without external TVS diodes. |
| XOR-Chain Board Test Support | On-die boundary-scan-like test structure - enables automated manufacturing test of interconnects without JTAG, reducing test fixture complexity and cost. |
Applications
| Desktop PC Motherboard Integration | Floppy-Based Industrial Control System |
|---|---|
Use Scenario: Consolidating legacy I/O and power management functions onto a single chip for ATX-form-factor desktop motherboards targeting Windows 2000/XP compatibility. IC Role / Device Role / Timing Role: Centralized LPC-based I/O hub managing keyboard/mouse, serial/parallel/floppy peripherals, fan monitoring, and platform power sequencing. Use Value: Reduces component count by >20 discrete ICs, cuts PCB area by ~15%, and guarantees BIOS-level compatibility with PC99a/PC2001 certification requirements. |
Use Scenario: Enabling floppy disk boot and firmware update capability in ruggedized industrial HMIs where USB is unsupported or unreliable. IC Role / Device Role / Timing Role: Floppy controller with 100% IBM 765B register compatibility and vertical recording support - handles media access, data separation, and error detection autonomously. Use Value: Eliminates need for external floppy controller ASIC or FPGA logic; supports 2.88 MB SuperDisk drives and detects all overrun/underrun conditions in real time. |
| Legacy Serial Device Gateway | ACPI-Compliant Embedded Platform |
Use Scenario: Connecting RS-232 modems, barcode scanners, and POS peripherals to modern embedded x86 platforms lacking native UART headers. IC Role / Device Role / Timing Role: Dual high-speed UART with 16-byte FIFOs, programmable baud generator, and full modem control (RTS/CTS/DTR/DCD) - operates up to 460 kbps. Use Value: Delivers deterministic latency and zero-drop communication under Windows/Linux interrupt load - avoids FIFO overflow even at 230 kbps with 10 ms polling intervals. |
Use Scenario: Implementing OS-directed power management in medical or kiosk devices requiring S3 suspend/resume and wake-on-keyboard events. IC Role / Device Role / Timing Role: ACPI 2.0-compliant power controller generating nRSMRST, PWRGD_PLATFORM, and PME signals - coordinates chipset, CPU, and peripheral power states. Use Value: Enables <100 ms resume-from-S3 latency and supports wake sources including keyboard, mouse, serial IRQ, and fan tachometer zero-crossing detection. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Advanced I/O controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W83627HF-AW | 208-pin QFP; integrates hardware monitor with temperature/voltage sensing; lacks ChiProtect and XOR-chain test. | Better suited for thermally monitored server boards; not drop-in due to pin count and missing SMBus isolation. | Select when real-time thermal telemetry is required and board layout allows larger package. |
| ITE IT8712F-A | 128-pin QFP; supports LPC but uses different configuration register map; no licensed 765B floppy core - relies on software emulation. | Lower cost for non-floppy applications; requires BIOS modification for IRQ/DMA remapping due to non-identical ISA PnP register layout. | Select only if floppy functionality is unused and BIOS vendor confirms register compatibility. |
Compared with Winbond W83627HF-AW and ITE IT8712F-A, the LPC47M182-NW uniquely combines 128-pin footprint efficiency, certified 765B floppy compliance, ChiProtect-enabled parallel port robustness, and hardware-accelerated XOR-chain test - making it the only option meeting strict PC99a/PC2001 desktop certification without layout or firmware compromise.
Availability
LPC47M182-NW is available at Aetrix Electronics and suitable for desktop motherboard design, legacy peripheral integration, industrial floppy-based control systems, ACPI-compliant embedded platforms, and PC99a-certified OEM production requiring stable component supply and long-term lifecycle support.
Supply support for LPC47M182-NW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a U.S.-based semiconductor manufacturer specializing in microcontrollers, analog devices, and interface solutions, with ISO/TS-16949-certified design and wafer fabrication facilities.
The LPC47M182-NW belongs to Microchip's Advanced I/O Controller product line, designed specifically to consolidate legacy PC I/O and motherboard GLUE logic into a single LPC-integrated device for cost-sensitive, certification-driven desktop and embedded x86 platforms.
FAQ
What is the operating voltage range and tolerance specification for the LPC47M182-NW?
The LPC47M182-NW operates at a nominal 3.3 V supply and is explicitly rated 5 V tolerant on all I/O pins per DS00001809A-page 1. This tolerance allows direct connection to legacy 5 V peripherals such as ISA-slot devices, parallel port printers, and PS/2 keyboards without external level shifters - a critical feature for backward compatibility in desktop motherboard designs.
Does the LPC47M182-NW include a hardware-based floppy disk controller, and what standards does it support?
Yes, the LPC47M182-NW integrates a licensed CMOS 765B floppy disk controller core that is fully register- and functionally compatible with the industry-standard Intel 8272 and NEC µPD765. It supports 2.88 MB Super I/O operation, vertical recording format, and detects all overrun and underrun conditions - delivering 100% IBM PC/XT/AT compatibility as confirmed in DS00001809A-page 2.
How many UARTs does the LPC47M182-NW provide, and what are their key performance characteristics?
The LPC47M182-NW includes two independent 16C550A-compatible UARTs, each with a 16-byte transmit/receive FIFO, programmable baud rate generator, and full modem control (RTS/CTS/DTR/DCD/RI/DSR). They support data rates up to 460 kbps and are explicitly validated for IrDA 1.0 compliance in the infrared port implementation per DS00001809A-page 1.
What power management standards and features are implemented in the LPC47M182-NW?
The LPC47M182-NW is fully compliant with ACPI 1.0b and 2.0 specifications and meets PC99a/PC2001 requirements. It provides hardware-generated nRSMRST, PWRGD_PLATFORM, and PME signals; supports S3/S5 sleep states; enables keyboard/mouse wake events; and includes sophisticated power control circuitry (PCC) with multiple low-power-down modes - all detailed in DS00001809A-page 2.
Is the LPC47M182-NW pin-compatible with other Microchip Super I/O devices such as the LPC47M192 or LPC47B272?
No, the LPC47M182-NW is not pin-compatible with the LPC47M192 or LPC47B272. While all belong to Microchip's LPC-based Super I/O family, the LPC47M182-NW uses a 128-pin QFP (NW) package with unique pin assignments for LAD[3:0], SER_IRQ, and GPIOs as shown in DS00001809A-page 5. Substitution requires PCB redesign and BIOS configuration updates due to differences in register mapping and feature enablement.
LPC47M182-NW Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 128-BQFP
- Packaging:
- Tray
- Product Status:
- Obsolete
- Applications:
- Controller
- Interface:
- LPC
- Voltage - Supply:
- 3.3V
- Supplier Device Package:
- 128-QFP (14x20)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
LPC47M182-NW FAQ
1.How can I place an order for LPC47M182-NW through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC47M182-NW on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC47M182-NW reliable?
The price and inventory of LPC47M182-NW are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC47M182-NW is usually 5 days.
3.What payment methods are accepted for LPC47M182-NW?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC47M182-NW transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC47M182-NW?
LPC47M182-NW orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC47M182-NW order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC47M182-NW?
For technical support, including LPC47M182-NW datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC47M182-NW requirements.
6.How does Aetrix verify that LPC47M182-NW is sourced from the original manufacturer or authorized distributors?
All LPC47M182-NW products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC47M182-NW meets industry standards.
7.What is the process for return or replacement of LPC47M182-NW?
All LPC47M182-NW units undergo pre-shipment inspection (PSI). If there is an issue with LPC47M182-NW, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC47M182-NW part is unused and in its original packaging.
Return procedure for LPC47M182-NW:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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