Microchip Technology LPC47M192-NW
- Part No.:
- LPC47M192-NW
- Manufacturer:
- Microchip Technology
- Category:
- Specialized
- Package:
- 128-BQFP
- Datasheet:
-
LPC47M192-NW.pdf
- Description:
- IC INTERFACE SPECIALIZED 128QFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LPC47M192-NW from SMSC is a 3.3V LPC-interface Super I/O controller with integrated hardware monitoring, fan control, dual UARTs, ECP/EPP parallel port, floppy disk controller (CMOS 765B core), and 8042-compatible keyboard/mouse controller - all in a 128-pin QFP package. It supports ACPI 1.0/2.0, PC99/PC2001 compliance, SMBus-accessible voltage/temperature monitoring (+1.5V to +12V, Vccp, internal/external thermal diodes), and two PWM fan outputs.
For engineers reviewing the LPC47M192-NW datasheet, LPC47M192-NW pinout, LPC47M192-NW application, or LPC47M192-NW equivalent, key selection criteria include LPC bus compatibility, hardware monitoring channel count (7 voltage inputs, 3 temperature sensors), legacy I/O integration (floppy, MIDI, game port), and lead-free 128-pin QFP packaging for industrial motherboard designs.
Technical Context
The LPC47M192-NW implements a unified LPC host interface with serialized IRQ and PME support, enabling direct connection to modern southbridge chipsets without ISA bus bridging. Its hardware monitoring block uses dedicated analog front-end circuitry with programmable thresholds and SMBus slave addressing (0x2C–0x2F) for real-time system health telemetry.
Legacy functionality is partitioned into logical devices: an 8042-based keyboard controller with 2 kB ROM/256 B RAM, dual 16C550A UARTs with 16-byte FIFOs, IEEE 1284-compliant parallel port (960 I/O address options), and a licensed CMOS 765B floppy controller supporting vertical recording, 16-byte FIFO, and 100% IBM PC/AT compatibility.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| LPC Interface | Fully compliant with LPC 1.1 spec; supports I/O, DMA, and memory-mapped cycles with CLOCKRUN/LPCPD power protocols. |
| Voltage Monitoring Inputs | 7 analog channels: +1.5V, +1.8V, +2.5V, +3.3V, +5V, +12V, Vccp - each with independent high/low limit registers and SMBus read capability. |
| Temperature Sensing | Internal ambient sensor + two external thermal diode inputs; configurable offset compensation per channel; THERM# assertion on out-of-limit condition. |
| Fan Control | Two PWM outputs (0–100% duty cycle) and two tachometer inputs with automatic RPM calculation and alarm threshold. |
| Floppy Controller | SMSC CMOS 765B core; software/register compatible with 82077AA; supports two drives, vertical recording, 16-byte FIFO, and full overrun/underrun detection. |
| UARTs | Dual 16C550A-compatible UARTs with 16-byte TX/RX FIFOs, programmable baud up to 460 kbps, and modem control logic. |
| Parallel Port | IEEE 1284-compliant ECP/EPP/Standard modes; ChiProtect circuitry; 960 I/O address options; three DMA channels supported. |
Pinout & Package
Package: 128-pin LQFP (20 × 20 mm, 0.4 mm pitch), green lead-free RoHS-compliant variant per ordering code LPC47M192-NW.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| LAD[3:0] | LPC Address/Data Bus | Multiplexed bidirectional 4-bit bus for LPC I/O, memory, and configuration cycles; requires external pull-up resistors. |
| LFRAME# | LPC Frame Signal | Indicates start of LPC transaction; active-low, synchronous to LCLK; used by host to initiate cycles. |
| LRESET# | Global Reset Input | Asynchronous active-low reset that clears internal registers and forces configuration mode on power-up. |
| nTHERM | Hardware Monitor Alert | Open-drain output asserted low when any monitored voltage or temperature exceeds programmed limits. |
| nRESET | System Reset Output | Drives 20 ms active-low pulse to motherboard reset line upon hardware monitor fault or watchdog timeout. |
| SMBCLK / SMBDATA | SMBus Interface | Open-drain bidirectional clock/data lines for hardware monitoring register access (slave address 0x2C–0x2F). |
| FANIN0 / FANIN1 | Fan Tachometer Inputs | Active-high pulse inputs measuring fan RPM via edge counting; support 2-wire or 3-wire fan feedback. |
| FANOUT0 / FANOUT1 | Fan PWM Outputs | Open-drain PWM signals (0–100% duty, 22 kHz default) driving external MOSFETs for variable-speed fan control. |
Key Features
| Feature | Design Value |
|---|---|
| ACPI 1.0/2.0 Compliance | Enables OS-directed power management including S0–S5 states, wake-on-keyboard/mouse, and SCI event generation without BIOS intervention. |
| ISA Plug-and-Play Register Set | Allows runtime reconfiguration of I/O base, IRQ, and DMA for each logical device (floppy, UARTs, parallel, etc.) via standard PnP registers. |
| Integrated Floppy Controller Core | True CMOS 765B implementation eliminates need for external floppy controller IC while maintaining full IBM PC/AT software compatibility. |
| ChiProtect Parallel Port Circuitry | On-die ESD protection and current limiting for IEEE 1284 signals, reducing external TVS requirements and improving robustness in industrial environments. |
| Programmable Thermal Offset | Per-channel ±15°C digital offset adjustment for external thermal diodes, compensating for PCB trace resistance and sensor placement error. |
Applications
| Industrial Motherboard Management | Legacy-Interface Embedded System |
|---|---|
Use Scenario: Fan-cooled industrial PC with dual CPU cooling zones, multi-rail power supply monitoring, and requirement for long-term BIOS/EC firmware stability. IC Role / Device Role / Timing Role: Centralized Super I/O managing hardware health telemetry, fan speed regulation, and legacy peripheral bridging via LPC bus. Use Value: Reduces BOM count by integrating 7-voltage monitoring, dual PWM fan control, and SMBus telemetry - eliminating discrete supervisor ICs and fan controllers. | Use Scenario: Medical imaging workstation requiring floppy disk boot media support, MIDI audio diagnostics, and parallel-port-connected legacy lab instruments. IC Role / Device Role / Timing Role: Legacy I/O hub providing 8042 keyboard/mouse, CMOS 765B floppy controller, MPU-401 MIDI UART, and ECP parallel port. Use Value: Maintains full backward compatibility with DOS/Windows CE firmware stacks while enabling modern LPC-based chipset integration. |
| PC99/PC2001-Compliant Desktop Platform | Thermal-Aware Server Management Module |
Use Scenario: Entry-level desktop motherboard targeting PC99/PC2001 certification with ACPI-compliant power sequencing and wake-on-LAN-ready design. IC Role / Device Role / Timing Role: System controller handling SMI generation, PME signaling, serial IRQ routing, and intelligent auto-power management for low idle power. Use Value: Delivers certified ACPI behavior (S3/S4 sleep/wake) and reduces platform validation effort through pre-verified register-level compliance. | Use Scenario: Rack-mounted server baseboard needing real-time core voltage (Vccp) and CPU die temperature monitoring with fail-safe reset assertion. IC Role / Device Role / Timing Role: Hardware monitor block acting as autonomous safety subsystem - independent of host CPU - asserting nTHERM/nRESET on overvoltage or thermal violation. Use Value: Provides deterministic 20 ms reset pulse and SMBus-accessible limit registers, enabling BMC-independent thermal shutdown for enhanced system reliability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Super I/O with hardware monitoring applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W83627HF | ISA-based interface (not LPC); lacks ACPI 2.0 support; 6 voltage inputs (no Vccp monitoring); single fan PWM output. | Requires ISA bus bridge; unsuitable for pure LPC platforms; limited thermal monitoring scope. | Select only for legacy ISA-based designs where LPC interface is unavailable. |
| Nuvoton NCT6776F | LPC interface; 10 voltage inputs (includes Vccp); dual thermal diode support; no integrated floppy controller or MIDI UART. | Modern replacement for hardware monitoring only; requires external floppy/MIDI solutions if those functions are needed. | Choose when legacy peripheral integration is unnecessary and higher channel-count monitoring is prioritized. |
Compared with LPC47M192-NW, W83627HF demands ISA infrastructure and offers reduced monitoring fidelity, while NCT6776F provides expanded voltage sensing but abandons integrated floppy/MIDI - making LPC47M192-NW uniquely suited for full-legacy LPC motherboard consolidation.
Availability
LPC47M192-NW is available at Aetrix Electronics and suitable for industrial motherboard management, legacy-interface embedded systems, and PC99/PC2001-compliant desktop platforms requiring stable component supply and long-lifecycle support.
Supply support for LPC47M192-NW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
SMSC (Standard Microsystems Corporation) was a fabless semiconductor company specializing in connectivity, embedded control, and system management ICs before its acquisition by Microchip Technology in 2012.
The LPC47M192-NW belongs to SMSC's LPC Super I/O product line, designed to consolidate legacy PC peripherals and hardware monitoring onto a single LPC-interfaced die for cost-sensitive, long-lifecycle industrial and embedded motherboards.
FAQ
What is the primary interface protocol used by the LPC47M192-NW?
The LPC47M192-NW uses the Low Pin Count (LPC) bus interface to communicate with the host chipset. It supports full LPC 1.1 functionality including I/O cycles, DMA transfers, serialized IRQ, and PME signaling - eliminating the need for an ISA bus and enabling direct integration with modern southbridges and PCHs. The LPC47M192-NW does not support ISA or PCI interfaces.
Does the LPC47M192-NW support Vccp (CPU core voltage) monitoring?
Yes, the LPC47M192-NW supports dedicated Vccp monitoring as one of its seven analog voltage inputs. This allows real-time tracking of processor core voltage with programmable high/low limits and SMBus-accessible readings - critical for thermal-aware power management in Pentium III/IV-era platforms. The LPC47M192-NW also monitors +1.5V, +1.8V, +2.5V, +3.3V, +5V, +12V, and HVSB.
Can the LPC47M192-NW replace older Super I/O chips like the SMSC FDC37C935?
The LPC47M192-NW is not a pin-compatible drop-in replacement for the FDC37C935 due to different package (128-pin QFP vs. 100-pin QFP) and LPC vs. ISA interface architecture. However, it provides functional superset capabilities - including enhanced hardware monitoring, ACPI 2.0 support, and SMBus access - making it a logical migration path for new LPC-based designs requiring broader legacy I/O integration than the FDC37C935 offers.
What fan control features does the LPC47M192-NW provide?
The LPC47M192-NW provides two independent PWM fan outputs (FANOUT0/FANOUT1) with 0–100% duty cycle control and two tachometer inputs (FANIN0/FANIN1) for RPM measurement. It calculates fan speed automatically, supports programmable alarm thresholds, and can assert nTHERM or trigger nRESET on fan failure - all configurable via SMBus or Super I/O runtime registers. The LPC47M192-NW does not include closed-loop PID control logic.
Is the LPC47M192-NW RoHS-compliant and lead-free?
Yes, the LPC47M192-NW is explicitly designated as a green, lead-free variant in SMSC's ordering information - confirmed by the "-NW" suffix denoting 128-pin QFP packaging with RoHS-compliant finish. It meets JEDEC J-STD-609A Class 3 marking requirements and is suitable for environmentally regulated industrial and commercial applications where lead-free assembly is mandated.
LPC47M192-NW Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 128-BQFP
- Packaging:
- Tray
- Product Status:
- Obsolete
- Applications:
- Controller
- Interface:
- LPC
- Voltage - Supply:
- 3.3V
- Supplier Device Package:
- 128-QFP (14x20)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
LPC47M192-NW FAQ
1.How can I place an order for LPC47M192-NW through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC47M192-NW on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC47M192-NW reliable?
The price and inventory of LPC47M192-NW are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC47M192-NW is usually 5 days.
3.What payment methods are accepted for LPC47M192-NW?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC47M192-NW transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC47M192-NW?
LPC47M192-NW orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC47M192-NW order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC47M192-NW?
For technical support, including LPC47M192-NW datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC47M192-NW requirements.
6.How does Aetrix verify that LPC47M192-NW is sourced from the original manufacturer or authorized distributors?
All LPC47M192-NW products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC47M192-NW meets industry standards.
7.What is the process for return or replacement of LPC47M192-NW?
All LPC47M192-NW units undergo pre-shipment inspection (PSI). If there is an issue with LPC47M192-NW, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC47M192-NW part is unused and in its original packaging.
Return procedure for LPC47M192-NW:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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