My Inquiry
My Account
Microchip Technology LPC47N267-MV
- Part No.:
- LPC47N267-MV
- Manufacturer:
- Microchip Technology
- Category:
- Specialized
- Package:
- 100-LQFP
- Datasheet:
-
LPC47N267-MV.pdf
- Description:
- IC INTFACE SPECIALIZED 100STQFP
- Quantity:
- Payment:
- Shipping:
Inventory:2,671
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC47N267-MV from SMSC is a 3.3 V, 100-pin STQFP Super I/O controller compliant with PC99 and ACPI 1.0b, integrating an LPC host interface, X-Bus peripheral expansion interface, 2.88 MB floppy disk controller (CMOS 765B core), two NS16C550-compatible UARTs with 16-byte FIFOs, and a multi-mode IEEE 1284 parallel port with ChiProtect - used in legacy-extended industrial PCs and embedded x86 platforms requiring integrated I/O consolidation.
For engineers reviewing the LPC47N267-MV datasheet, LPC47N267-MV pinout, LPC47N267-MV application, or LPC47N267-MV equivalent, key selection considerations include its X-Bus support for up to four external components, 29 GPIOs, programmable Wakeup Event (IO_PME#) and SMI (IO_SMI#) signaling, 8-bit I/O transfers over LPC/X-Bus, and ACPI-compliant power management with multiple low-power down modes.
Technical Context
The LPC47N267-MV implements a multiplexed LPC bus interface supporting I/O cycles only (no memory access), serial IRQ signaling compatible with PCI systems, and nCLKRUN support. Its X-Bus interface provides 16-bit address qualification, write protection per component, and three operational modes - all accessed via LPC configuration registers.
Internally, it integrates a licensed CMOS 765B floppy controller with vertical recording support, advanced digital data separator enabling 2 Mbps/1 Mbps/500 kbps data rates, and dual UARTs - one with IrDA v1.2 (4 Mbps), HPSIR, ASKIR, and Consumer IR support. All peripherals are software-configurable via internal registers and ACPI-compliant power states.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| LPC Interface | 8-bit I/O and DMA transfers; 16-bit address qualification; serial IRQ and nCLKRUN support for PCI compatibility |
| X-Bus Interface | Supports up to 4 external components; 8-bit data width; write-protect per component; no memory cycle support |
| Floppy Controller | 2.88 MB capacity; CMOS 765B core; 100% IBM PC/AT compatibility; 16-byte FIFO; vertical recording at 1 Mbps |
| UARTs | Two NS16C550-compatible ports; 16-byte TX/RX FIFOs; baud rates up to 460 kbps; one supports IrDA v1.2 (4 Mbps) |
| Parallel Port | IEEE 1284 EPP 1.7/1.9 and ECP compliant; ChiProtect circuitry prevents printer-power-on damage |
| GPIO & Interrupts | 29 general-purpose I/O pins; four IRQ input pins; IO_PME# and IO_SMI# dedicated event signaling pins |
| Power & Compliance | 3.3 V operation (5 V tolerant); PC99 and ACPI 1.0b compliant; multiple hardware power-down modes via PCC |
Pinout & Package
Package: 100-pin STQFP (12 mm × 12 mm body, 1.4 mm height, 0.4 mm pitch), JEDEC MS-026 compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| LAD0–LAD3 | LPC Bus Data/Address | Multiplexed 4-bit command/address/data lines for LPC interface communication |
| nLFRAME | LPC Frame Signal | Indicates start of LPC transaction; synchronizes host-to-device command framing |
| nLDRQ | LPC DMA Request | Asserted by LPC47N267-MV to request DMA service from host; supports three configurable DMA channels |
| IO_PME# | Power Management Event | Open-drain output signaling wake-up events to host chipset; ACPI-compliant PME assertion |
| IO_SMI# | System Management Interrupt | Open-drain output triggering SMI entry for firmware-controlled system management functions |
| XD0–XD7 | X-Bus Data | 8-bit bidirectional data bus for I/O cycles to up to four external X-Bus peripherals |
| XCS0#–XCS3# | X-Bus Chip Select | Four independent active-low chip selects; each with write-protected base address and enable control |
| XRD#, XWR# | X-Bus Read/Write | Active-low strobes controlling direction and timing of X-Bus I/O transfers |
| XA0–XA3 | X-Bus Address | 4-bit address bus qualifying up to 16 I/O locations per X-Bus component |
| GP10*–GP47* | General Purpose I/O | 29 configurable GPIOs; many multifunction (e.g., FDC_PP*, IRQIN1*–IRQIN4*) with pull-up/pull-down options |
Key Features
| Feature | Design Value |
|---|---|
| Software-Configurable Logic (SCL) | Enables runtime reconfiguration of FDC, UART, and parallel port settings without hardware changes |
| ChiProtect Parallel Port Circuitry | Prevents latch-up or damage when hot-plugging powered printers by isolating Vcc-sensitive logic |
| Advanced Digital Data Separator | Supports 2 Mbps/1 Mbps/500 kbps/300 kbps/250 kbps floppy data rates with programmable precompensation |
| X-Bus Write Protection | BIOS-only write access to component base addresses and disable bits prevents malware-induced corruption |
| ACPI 1.0b Power Management | Hardware-enforced low-power down modes coordinated via ACPI _PSC and _PS0/_PS3 methods |
| IrDA v1.2 + Consumer IR Support | Single UART supports Fast IR (4 Mbps), HPSIR, ASKIR, and generic remote-control protocols without external PHY |
Applications
| Industrial Embedded PC | Legacy-Extended Thin Client |
|---|---|
|
Use Scenario: Fanless x86-based controller board in factory automation, requiring long-life I/O consolidation and BIOS-level power control. IC Role / Device Role / Timing Role: Central Super I/O hub managing floppy boot, serial diagnostics, parallel printer interface, and wake-on-event triggers. Use Value: Eliminates discrete UART, FDC, and parallel port ICs; reduces BOM count and PCB area while maintaining full IBM PC/AT register compatibility. |
Use Scenario: Low-cost thin client deploying Windows CE or DOS-based terminal firmware with local printer and serial console support. IC Role / Device Role / Timing Role: Integrated I/O subsystem providing EPP/ECP parallel port, dual high-speed UARTs, and ACPI-compliant suspend/resume. Use Value: Enables single-chip I/O for legacy peripheral attachment without external level shifters or glue logic - critical for cost-sensitive designs. |
| Secure Boot Platform | Medical Diagnostic Instrument |
|
Use Scenario: Trusted computing module requiring BIOS-controlled write protection for boot-critical peripherals and tamper-resistant configuration. IC Role / Device Role / Timing Role: Secure I/O controller enforcing X-Bus component lockdown and SMI-triggered firmware validation routines. Use Value: Hardware-enforced write protection on X-Bus base addresses prevents unauthorized modification of peripheral mappings during boot. |
Use Scenario: Portable ultrasound or patient monitor needing reliable serial debug, infrared remote control, and floppy-based firmware update capability. IC Role / Device Role / Timing Role: Multi-protocol I/O interface handling IrDA v1.2 remote commands, UART-based sensor telemetry, and FDC-based field updates. Use Value: Single-chip support for IR remote, serial diagnostics, and legacy firmware loading avoids adding discrete transceivers or controllers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Super I/O controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W83627HF | 128-pin LQFP; lacks X-Bus interface; includes hardware monitor and fan control not present in LPC47N267-MV | Targeted at desktop motherboards with thermal monitoring needs; no X-Bus peripheral expansion capability | Select when thermal sensing and fan PWM control are required, and X-Bus expansion is unnecessary |
| Nuvoton NCT6776D | 128-pin QFN; adds SMBus host controller and enhanced ACPI 5.0 support; no floppy controller or X-Bus | Designed for modern UEFI-based platforms requiring hardware monitoring and secure boot coordination | Select for ACPI 5.0+ systems needing hardware monitor integration, not legacy floppy or X-Bus peripheral support |
Compared with Winbond W83627HF and Nuvoton NCT6776D, the LPC47N267-MV uniquely delivers X-Bus expansion for up to four external peripherals and native 2.88 MB floppy support - making it irreplaceable in legacy-extended industrial PCs where those features are mandatory.
Availability
LPC47N267-MV is available at Aetrix Electronics and suitable for industrial embedded PCs, legacy-extended thin clients, secure boot platforms, and medical diagnostic instruments requiring stable component supply and long-term availability.
Supply support for LPC47N267-MV includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
SMSC (Standard Microsystems Corporation) was a fabless semiconductor company specializing in connectivity, embedded control, and I/O solutions before its acquisition by Microchip Technology in 2012.
The LPC47N267-MV belongs to SMSC's LPC Super I/O product line, designed specifically for x86-based industrial and embedded systems requiring consolidated legacy I/O, ACPI-compliant power management, and BIOS-controllable peripheral expansion via X-Bus.
FAQ
What is the operating voltage range for the LPC47N267-MV?
The LPC47N267-MV operates at 3.3 V nominal supply with 5 V tolerance on all I/O pins. This allows direct interfacing with legacy 5 V peripherals without level-shifting circuitry, while maintaining low-power operation essential for thermally constrained embedded platforms. The LPC47N267-MV does not support 5 V core operation - only I/O pins are 5 V tolerant.
Does the LPC47N267-MV support floppy disk drives beyond standard 1.44 MB capacity?
Yes, the LPC47N267-MV supports 2.88 MB high-density floppy drives via its licensed CMOS 765B floppy disk controller core. It enables vertical recording format at 1 Mbps data rate and includes full overrun/underrun detection, drive swap (A/B), and forceable write-protect controls - all accessible through standard IBM PC/AT register maps used by the LPC47N267-MV.
Can the X-Bus interface of the LPC47N267-MV be used for memory-mapped peripherals?
No, the X-Bus interface of the LPC47N267-MV supports I/O cycles only - memory-mapped access is explicitly unsupported. The X-Bus provides 8-bit data transfer, 16-bit address qualification, and four chip-select outputs (XCS0#–XCS3#), but all transactions must be initiated as I/O port accesses through the LPC interface configuration registers of the LPC47N267-MV.
How many interrupt resources does the LPC47N267-MV provide for system use?
The LPC47N267-MV provides four dedicated IRQ input pins (IRQIN1#–IRQIN4#) for external device interrupts, plus programmable Serial IRQ output compatible with PCI systems. Each on-chip peripheral (FDC, UARTs, parallel port) can be assigned one of 15 configurable hardware IRQ lines via internal configuration registers - a capability fully implemented in the LPC47N267-MV's ACPI-compliant resource allocation.
Is the LPC47N267-MV pin-compatible with other SMSC Super I/O devices like the LPC47M192?
No, the LPC47N267-MV is not pin-compatible with the LPC47M192 or other members of the LPC47 family. It uses a unique 100-pin STQFP footprint with distinct pin assignments for X-Bus signals (XD0–XD7, XCS0#–XCS3#, XRD#, XWR#), which are absent in earlier variants. Board layout must be designed specifically for the LPC47N267-MV package and signal mapping.
LPC47N267-MV Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 100-LQFP
- Packaging:
- Tray
- Product Status:
- Obsolete
- Applications:
- Controller
- Interface:
- LPC
- Voltage - Supply:
- 3.3V
- Supplier Device Package:
- 100-STQFP (12x12)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
LPC47N267-MV FAQ
1.How can I place an order for LPC47N267-MV through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC47N267-MV on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC47N267-MV reliable?
The price and inventory of LPC47N267-MV are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC47N267-MV is usually 5 days.
3.What payment methods are accepted for LPC47N267-MV?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC47N267-MV transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC47N267-MV?
LPC47N267-MV orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC47N267-MV order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC47N267-MV?
For technical support, including LPC47N267-MV datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC47N267-MV requirements.
6.How does Aetrix verify that LPC47N267-MV is sourced from the original manufacturer or authorized distributors?
All LPC47N267-MV products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC47N267-MV meets industry standards.
7.What is the process for return or replacement of LPC47N267-MV?
All LPC47N267-MV units undergo pre-shipment inspection (PSI). If there is an issue with LPC47N267-MV, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC47N267-MV part is unused and in its original packaging.
Return procedure for LPC47N267-MV:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC47N267-MV Tags
-
NVT4857UKAZ
NXP Semiconductors
-
TCA8418RTWR
Texas Instruments
-
PCA9546APWR
Texas Instruments
-
MD0100N8-G
Microchip Technology
-
PCA9548APW,118
NXP Semiconductors
-
PCA9540BDP,118
NXP Semiconductors
-
PCA9548APWR
Texas Instruments
-
PCA9546APW,118
NXP Semiconductors
-
PTN3360DBS,518
NXP Semiconductors
-
PCA9546ABS,118
NXP Semiconductors
-
PCA9518PWR
Texas Instruments
-
PCA9545APW,118
NXP Semiconductors
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
