My Inquiry
My Account
Microchip Technology LPC47S422-MS
- Part No.:
- LPC47S422-MS
- Manufacturer:
- Microchip Technology
- Category:
- Specialized
- Package:
- 100-BQFP
- Datasheet:
-
LPC47S422-MS.pdf
- Description:
- IC INTERFACE SPECIALIZED 100QFP
- Quantity:
- Payment:
- Shipping:
Inventory:1,040
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC47S422-MS from SMSC is a 3.3 V PC99- and ACPI 1.0-compliant Enhanced Super I/O controller with LPC interface, integrating two NS16C550-compatible UARTs (16-byte FIFO), a CMOS 765B floppy disk controller, multi-mode IEEE 1284 parallel port with ChiProtect™, SMBus controller, 39 GPIOs, fan speed control/tachometer, and X-Bus interface - deployed in server motherboard I/O hub functions.
For engineers reviewing the LPC47S422-MS datasheet, LPC47S422-MS pinout, LPC47S422-MS application, or LPC47S422-MS equivalent, key selection criteria include LPC bus compatibility, ISA Plug-and-Play register set support, 480 I/O address options, serial IRQ routing capability, and RoHS-compliant 100-pin QFP packaging for legacy server platform integration.
Technical Context
The LPC47S422-MS implements a pin-reduced LPC interface replacing ISA/X-bus while maintaining full software compatibility with Windows '95/'98 and PC99 requirements. It embeds an 8-bit 8042-compatible keyboard microcontroller with 2 KB ROM and 256 B RAM, plus hardware logic for Port 92, Gate A20, and KRESET.
Its integrated digital data separator supports five programmable data rates (2 Mbps to 250 Kbps) with precompensation modes, and its parallel port delivers EPP 1.7/1.9 and ECP modes under IEEE 1284, with multiplexed command/address/data bus and 16-bit address qualification.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Voltage Supply | 3.3 V operation with 5 V tolerant I/O pins - enables direct interfacing with legacy 5 V peripherals without level shifters. |
| LPC Interface | Pin-reduced LPC bus compliant with Intel specification - replaces ISA/X-bus with reduced footprint and maintained performance. |
| Floppy Controller | CMOS 765B core supporting 2.88 MB format, 16-byte FIFO, overrun/underrun detection - ensures full IBM PC/AT compatibility and robust FDC operation. |
| UARTs | Two NS16C550-compatible UARTs with 16-byte send/receive FIFOs and IrDA 1.0/HP-SIR/ASK IR support - enables high-throughput serial communication up to 460 kbaud. |
| Parallel Port | IEEE 1284-compliant multi-mode port (Standard, EPP, ECP) with ChiProtect™ circuitry - prevents damage during printer power-on sequences in server peripheral stacks. |
| Power Management | Intelligent Auto Power Management with multiple low-power down modes and PCC circuitry - reduces idle power in server baseboard management subsystems. |
| GPIO Count | 39 general-purpose I/O pins - provides flexible board-level control, status monitoring, and hardware configuration signaling. |
| Package | 100-pin lead-free RoHS-compliant QFP - meets environmental compliance mandates for enterprise server manufacturing. |
Pinout & Package
Package: 100-pin Quad Flat Package (QFP), lead-free, RoHS-compliant, body dimensions 24.0 mm × 24.0 mm (D/E), 0.65 mm pitch, 3.0 mm max height (A), coplanarity ≤ 0.10 mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| LPC_CLK | LPC Interface Clock Input | Accepts 33 MHz system clock for synchronous LPC bus timing and device synchronization. |
| LPC_FRAME# | LPC Frame Signal | Indicates start/end of LPC transaction cycle; active-low, open-drain compatible. |
| LPC_AD[0:3] | LPC Address/Data Multiplexed Bus | Time-multiplexed 4-bit address/data path for configuration and I/O access over LPC interface. |
| nIO_SMI | System Management Interrupt Output | Asserts SMI# signal to host CPU upon configured system management events (e.g., thermal alert). |
| nIO_PME | Power Management Event Output | Drives PME# signal to enable wake-from-suspend via LPC or PCI-serialized IRQ paths. |
| FAN_TACH | Fan Tachometer Input | Monitors fan RPM via pulse counting on open-collector input; supports 2–4 pulse per revolution decoding. |
| FAN_PWM | Fan Speed Control Output | Generates variable-duty-cycle PWM signal (25 kHz typical) to regulate 4-wire fan speed. |
| SMBCLK / SMBDAT | SMBus Interface Signals | Supports SMBus 2.0 master/slave communication for temperature sensors, EEPROMs, and PMBus devices. |
Key Features
| Feature | Design Value |
|---|---|
| ISA Plug-and-Play Register Set | Software-configurable I/O address (480 options), IRQ (15 options), and DMA channel (3 options) per logical device - eliminates DIP-switch configuration in server BIOS setup. |
| Serialized IRQ Interface | Routes four ISA IRQs to any of eight serial IRQ lines - enables scalable interrupt handling in PCI-based server platforms with limited physical IRQ lines. |
| ChiProtect™ Circuitry | Integrated clamping and current-limiting on parallel port pins - prevents latch-up or damage when hot-plugging powered printers or scanners. |
| Advanced Digital Data Separator | Programmable data rate (250–2000 Kbps) and precompensation modes - ensures reliable floppy read/write across varying media quality and drive aging. |
| Intelligent Power Control (PCC) | Multiple hardware-controlled power-down modes including standby, suspend, and deep sleep - reduces quiescent current to <100 µA in server baseboard management controllers. |
Applications
| Server Baseboard Management | Legacy Industrial Control Panel |
|---|---|
Use Scenario: Embedded controller on x86 server motherboard providing legacy I/O for BMC, BIOS, and service processor interfaces. IC Role / Device Role / Timing Role: Centralized Super I/O hub managing floppy, serial, parallel, keyboard, fan, and SMBus peripherals via LPC bus. Use Value: Enables PC99/ACPI 1.0 compliance and Windows '98/2000 driver support without discrete logic or additional glue ICs. | Use Scenario: Retrofit I/O expansion for aging PLC or HMI systems requiring floppy boot, serial diagnostics, and parallel printer output. IC Role / Device Role / Timing Role: Drop-in replacement for obsolete 82077AA+8042+UART+parallel combo chips in ISA-based industrial controllers. Use Value: Maintains full IBM PC/AT software compatibility while adding fan monitoring and SMBus sensor integration. |
| Embedded Storage Appliance Controller | Network Appliance Console Interface |
Use Scenario: I/O co-processor in NAS/SAN appliances handling local diagnostics, firmware update via floppy/serial, and thermal management. IC Role / Device Role / Timing Role: Dedicated I/O manager offloading host CPU from low-speed peripheral polling and interrupt servicing. Use Value: Reduces host CPU interrupt load by >70% through hardware FIFO buffering and serialized IRQ aggregation. | Use Scenario: Console I/O subsystem in firewall/routing appliances providing CLI access, boot logging, and out-of-band management via serial port and SMBus-connected sensors. IC Role / Device Role / Timing Role: Dual UART + SMBus + GPIO hub enabling simultaneous console session, debug trace, and thermal shutdown signaling. Use Value: Supports concurrent IrDA 1.0 and HP-SIR infrared console access while maintaining secure, isolated serial management channel. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Super I/O controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W83627HF | 24-pin LPC interface, 128-byte UART FIFOs, no ChiProtect™, supports only EPP/ECP (no Standard mode) | Targeted at desktop motherboards; lacks fan tachometer input and X-Bus interface | Preferred where larger UART buffers and lower cost are prioritized over server-grade reliability features |
| Nuvoton NCT6776F | Integrated hardware monitor with 12-bit ADC, 64-byte UART FIFOs, supports AMI MegaRAID BIOS extensions | Designed for modern UEFI-based servers; requires updated ACPI tables and lacks 8042 keyboard ROM | Recommended for new designs needing real-time voltage/temp monitoring but not legacy 8042 firmware dependency |
Compared with LPC47S422-MS, the W83627HF offers higher UART throughput but omits fan tachometer and ChiProtect™, while the NCT6776F adds precision monitoring yet removes embedded 8042 ROM - making LPC47S422-MS uniquely suited for BIOS-dependent server platforms requiring full IBM compatibility and robust peripheral protection.
Availability
LPC47S422-MS is available at Aetrix Electronics and suitable for server baseboard design, legacy industrial control retrofit, and embedded storage appliance development requiring stable component supply and long-term lifecycle support.
Supply support for LPC47S422-MS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
SMSC (Standard Microsystems Corporation) was a fabless semiconductor company specializing in connectivity, embedded control, and mixed-signal ICs before its acquisition by Microchip Technology in 2012.
The LPC47S422-MS belongs to SMSC's Enhanced Super I/O product line, engineered specifically for x86 server and workstation platforms requiring PC99/ACPI 1.0 compliance, legacy peripheral support, and integrated power management.
FAQ
What is the primary interface protocol used by the LPC47S422-MS?
The LPC47S422-MS uses the Low Pin Count (LPC) interface as its primary host-to-peripheral communication bus. This interface replaces the legacy ISA/X-bus with a 4-pin multiplexed address/data bus (LPC_AD[0:3]), frame signal (LPC_FRAME#), clock (LPC_CLK), and reset (LPC_RST#). The LPC47S422-MS fully complies with Intel's LPC specification and maintains backward compatibility with ISA Plug-and-Play register mapping, enabling seamless integration into x86 server chipsets without requiring changes to BIOS or OS drivers.
Does the LPC47S422-MS support both EPP and ECP parallel port modes?
Yes, the LPC47S422-MS supports IEEE 1284-compliant Enhanced Parallel Port (EPP) versions 1.7 and 1.9, as well as Enhanced Capabilities Port (ECP) mode. Its multi-mode parallel port also retains Standard (IBM PC/XT/AT/PS/2) bidirectional compatibility. The LPC47S422-MS implements ChiProtect™ circuitry to safeguard against electrical damage during printer power-on sequences - a feature critical for server environments where hot-plug peripheral events occur. All modes share the same 480 I/O address space and support up to three DMA channels.
How many UARTs does the LPC47S422-MS integrate, and what are their key capabilities?
The LPC47S422-MS integrates two full-function UARTs compatible with the NS16C550 architecture. Each UART includes independent 16-byte transmit and receive FIFOs, programmable baud rate generation supporting up to 460 kbaud, modem control signals (CTS/RTS/DSR/DTR), and IrDA 1.0, HP-SIR, and ASK IR physical layer support. Both UARTs operate under the same 480 I/O address space and support 15 configurable IRQ options, allowing flexible routing to serial IRQ lines in PCI-based server platforms.
Is the LPC47S422-MS compatible with Windows operating systems?
Yes, the LPC47S422-MS is explicitly designed to support Windows '95, '98, and 2000 through full PC99 and ACPI 1.0 compliance. Its ISA Plug-and-Play register set allows dynamic resource allocation (I/O address, IRQ, DMA) during OS boot, and its embedded 8042 keyboard controller includes 2 KB of ROM with standard IBM-compatible firmware. The LPC47S422-MS also supports SMI# and PME# signaling required for advanced power management in Windows-based server environments.
What fan control features are implemented in the LPC47S422-MS?
The LPC47S422-MS provides dedicated hardware for thermal management: one PWM output (FAN_PWM) for closed-loop fan speed control and one tachometer input (FAN_TACH) for RPM monitoring. The PWM operates at ~25 kHz with adjustable duty cycle via internal registers, and the tachometer input supports 2–4 pulses per revolution decoding. These signals are fully integrated into the Intelligent Power Management engine, enabling automatic fan response to temperature thresholds defined in SMBus-connected thermal sensors or BIOS-configured profiles - all without host CPU intervention.
LPC47S422-MS Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 100-BQFP
- Packaging:
- Tray
- Product Status:
- Obsolete
- Applications:
- Controller
- Interface:
- LPC
- Voltage - Supply:
- 3.3V
- Supplier Device Package:
- 100-QFP
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
LPC47S422-MS FAQ
1.How can I place an order for LPC47S422-MS through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC47S422-MS on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC47S422-MS reliable?
The price and inventory of LPC47S422-MS are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC47S422-MS is usually 5 days.
3.What payment methods are accepted for LPC47S422-MS?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC47S422-MS transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC47S422-MS?
LPC47S422-MS orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC47S422-MS order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC47S422-MS?
For technical support, including LPC47S422-MS datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC47S422-MS requirements.
6.How does Aetrix verify that LPC47S422-MS is sourced from the original manufacturer or authorized distributors?
All LPC47S422-MS products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC47S422-MS meets industry standards.
7.What is the process for return or replacement of LPC47S422-MS?
All LPC47S422-MS units undergo pre-shipment inspection (PSI). If there is an issue with LPC47S422-MS, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC47S422-MS part is unused and in its original packaging.
Return procedure for LPC47S422-MS:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC47S422-MS Tags
-
NVT4857UKAZ
NXP Semiconductors
-
TCA8418RTWR
Texas Instruments
-
PCA9546APWR
Texas Instruments
-
MD0100N8-G
Microchip Technology
-
PCA9548APW,118
NXP Semiconductors
-
PCA9540BDP,118
NXP Semiconductors
-
PCA9548APWR
Texas Instruments
-
PCA9546APW,118
NXP Semiconductors
-
PTN3360DBS,518
NXP Semiconductors
-
PCA9546ABS,118
NXP Semiconductors
-
PCA9518PWR
Texas Instruments
-
PCA9545APW,118
NXP Semiconductors
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
