NXP Semiconductors LPC54113J128BD64Y

Overview

LPC54113J128BD64Y from NXP Semiconductors is a dual-core ARM Cortex-M4/M0+ microcontroller in LQFP64 package, featuring 128 KB flash, 96 KB SRAM (32 KB SRAMX + 64 KB SRAM0), 12-bit 5.0 MS/s ADC with 12 input channels, crystal-less USB 2.0 full-speed device interface, and DMIC subsystem for PDM microphone processing - deployed in industrial voice-enabled edge nodes and low-power sensor hubs.

For engineers reviewing the LPC54113J128BD64Y datasheet, LPC54113J128BD64Y pinout, LPC54113J128BD64Y application, or LPC54113J128BD64Y equivalent, key selection criteria include dual-core real-time partitioning capability, USB crystal-less operation support, integrated temperature sensor, Flexcomm configurable serial interfaces, and -40 °C to +105 °C extended temperature grade.

Technical Context

The LPC54113J128BD64Y implements two independent 32-bit ARM cores: Cortex-M4 running at up to 150 MHz with FPU and MPU, and Cortex-M0+ operating at up to 150 MHz on the same clock domain. Core isolation enables deterministic real-time task offloading while maintaining toolchain compatibility.

Its peripheral architecture centers on eight Flexcomm interfaces (FC0–FC7), each software-configurable as USART, SPI, or I2C; FC6 and FC7 also support I2S. The DMIC subsystem includes dual-channel PDM input, hardware decimation, FIFO buffering, and optional voice activity detection - enabling direct digital microphone integration without external codecs.

Key Specifications

Pinout & Package

LQFP64 package: plastic low-profile quad flat package, 64 leads, body size 10 × 10 × 1.4 mm (SOT314-2), lead pitch 0.5 mm, RoHS-compliant, rated for -40 °C to +105 °C operation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core ARM microcontroller applications.

Compared with LPC54114J256BD64, the LPC54113J128BD64Y trades flash/SRAM capacity for lower cost and power in resource-constrained edge nodes; versus LPC55S16JBD64, it prioritizes real-time dual-core flexibility over cryptographic acceleration and TrustZone.

Availability

LPC54113J128BD64Y is available at Aetrix Electronics and suitable for industrial sensor hubs, USB-connected edge gateways, and low-power smart thermostats requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for LPC54113J128BD64Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with headquarters in Eindhoven, Netherlands.

The LPC5411x product line targets high-efficiency, dual-core embedded applications demanding real-time responsiveness, low-power operation, and rich analog/digital peripheral integration - especially voice, sensor fusion, and USB device endpoints.

FAQ

What is the maximum operating frequency of the LPC54113J128BD64Y cores?

The LPC54113J128BD64Y supports both ARM Cortex-M4 and Cortex-M0+ cores at up to 150 MHz. This frequency is achievable using the internal 96 MHz FRO with system PLL multiplication or an external clock source up to 25 MHz. The cores share the same clock domain, ensuring synchronized operation without inter-core timing skew. All timing-critical peripherals - including the 5.0 MS/s ADC and SCTimer/PWM - are fully functional at this rate.

Does the LPC54113J128BD64Y support crystal-less USB operation?

Yes, the LPC54113J128BD64Y integrates a full-speed USB 2.0 device controller with on-chip PHY and supports crystal-less operation in device mode using NXP's software library (documented in Technical Note TN00031). It derives USB timing from the internal 48 MHz FRO output, eliminating the need for an external 12 MHz crystal and associated passive components - reducing BOM cost and PCB area.

How much SRAM is available on the LPC54113J128BD64Y, and how is it allocated?

The LPC54113J128BD64Y provides 96 KB total SRAM: 32 KB SRAMX (on I&D buses), 64 KB SRAM0 (contiguous main SRAM), with no SRAM1 or SRAM2 allocation per the official ordering table. This configuration optimizes memory bandwidth for dual-core operation - SRAMX serves instruction/data caching for M4, while SRAM0 supports general-purpose buffers, stack, and heap for both cores via the multilayer AHB matrix.

Which pins on the LPC54113J128BD64Y support analog input for the 12-bit ADC?

The LPC54113J128BD64Y supports 12 ADC input channels mapped to GPIO pins PIO0_29 through PIO1_5 (ADC0_0 to ADC0_8), plus three additional channels accessible via internal sources (temperature sensor, bandgap, VREFP). Each pin requires the DIGIMODE bit cleared in its IOCON register to enable analog functionality. All 12 channels support hardware-triggered conversions at up to 5.0 MSamples/sec with dual independent sequence control.

What debug interfaces are supported by the LPC54113J128BD64Y?

The LPC54113J128BD64Y supports Serial Wire Debug (SWD) via dedicated SWDIO and SWCLK pins (mapped to PIO0_17 and PIO0_16), with six instruction breakpoints, two literal comparators, and four watchpoints on the M4 core; the M0+ core offers four breakpoints and two watchpoints. JTAG boundary scan is also supported for production testing. SWO trace output is available on PIO0_15 for real-time program flow analysis.