NXP Semiconductors LPC54113J256UK49Z
- Part No.:
- LPC54113J256UK49Z
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 49-UFBGA, WLCSP
- Datasheet:
-
LPC54113J256UK49Z.pdf
- Description:
- IC MCU 32BIT 256KB FLASH 49WLCSP
- Quantity:
- Payment:

- Shipping:

Inventory:4,153
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC54113J256UK49Z from NXP Semiconductors is a dual-core ARM Cortex-M4/M0+ microcontroller for low-power embedded applications, featuring 256 KB flash, 192 KB SRAM, crystal-less USB 2.0 full-speed device interface, 12-bit 5.0 MS/s ADC, and integrated DMIC subsystem with PDM microphone support. It operates across −40 °C to +105 °C and targets voice-enabled edge nodes, industrial sensor hubs, and USB-connected IoT endpoints.
For engineers reviewing the LPC54113J256UK49Z datasheet, LPC54113J256UK49Z pinout, LPC54113J256UK49Z application, or LPC54113J256UK49Z equivalent, key selection considerations include dual-core real-time partitioning, WLCSP49 package constraints, crystal-less USB timing compliance, DMIC subsystem resource allocation, and Flexcomm interface multiplexing flexibility.
Technical Context
The LPC54113J256UK49Z integrates two independent 32-bit processors: the Cortex-M4 (with FPU and MPU) and Cortex-M0+ (code- and tool-compatible), both running up to 150 MHz from a shared clock source. Its memory subsystem includes 256 KB on-chip flash with page erase, 192 KB distributed SRAM (SRAMX/SRAM0/SRAM1/SRAM2), and ROM-based USB drivers supporting HID/CDC/MSC/DFU.
Peripherals are organized around an AHB matrix and APB bridges, with eight Flexcomm interfaces (each configurable as USART/SPI/I2C, two with I2S), a dedicated DMIC subsystem with hardware voice activity detection, and a 24-bit multi-rate timer (MRT) for deterministic interrupt scheduling. Power management includes programmable PMU, deep power-down mode, and wake-up via USB, USART, SPI, or I2C slave activity.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual ARM Cortex-M4 (150 MHz, FPU/MPU) + Cortex-M0+ (150 MHz, single-cycle I/O) |
| Memory | 256 KB flash (256-byte page erase); 192 KB SRAM (32 KB SRAMX + 64 KB ×2 SRAM0/SRAM1 + 32 KB SRAM2) |
| Analog | 12-bit ADC with 12 channels, 5.0 MS/s sample rate, dual conversion sequences, internal temperature sensor |
| Digital Audio | DMIC subsystem: dual-channel PDM input, hardware decimation, 16-entry FIFO, optional DC locking, VAD, I2S streaming |
| USB Interface | Full-speed (12 Mbps) device controller with on-chip PHY and crystal-less operation using software library (TN00031) |
| Serial Peripherals | Eight Flexcomm interfaces (FC0–FC7): each configurable as USART/SPI/I2C; FC6/FC7 add I2S; fractional baud-rate generator shared |
| Package | WLCSP49 (7×7 bumps, 3.436 × 3.436 × 0.525 mm, 0.4 mm pitch) |
Pinout & Package
WLCSP49 package: wafer-level chip-scale, 49-bump array (7×7), 0.4 mm pitch, body size 3.436 × 3.436 × 0.525 mm. Bump A1 is pin #1 index area.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1 | PIO0_23 / TMS | General-purpose I/O; default TMS in JTAG boundary scan; FC1 I2C SCL in ISP mode |
| B1 | PIO1_1 / ADC0_4 | ADC input channel 4; SWO trace output; FC5 SPI SSEL2; FC4 USART TXD |
| C1 | PIO0_30 / ADC0_1 | ADC input channel 1; FC1 USART TXD; SCT0 PWM output 3 |
| D1 | VSS | Digital ground reference for core logic and I/O banks |
| E1 | PIO0_26 | GPIO with FC4 CTS/SDA/SSEL0 function; CTimer0 capture input 3 |
| F1 | PIO0_24 | GPIO with FC1 I2C SDA in ISP mode; CTimer0 capture input 1 |
| G1 | VDD | Core power supply (1.62–3.6 V); decoupled per bump group |
| A2 | PIO1_4 / ADC0_7 | ADC input channel 7; PDM1_CLK output; FC7 USART RTS; SCT0 PWM output 7 |
| B2 | PIO1_2 / ADC0_5 | ADC input channel 5; MCLK I/O for I2S/PDM; FC7 SPI SSEL3 |
| C2 | PIO0_31 / ADC0_2 | ADC input channel 2; PDM0_CLK output; FC2 CTS/SDA/SSEL0; ISP boot trigger |
| D2 | VSSA | Analog ground, isolated for ADC/temperature sensor reference stability |
| E2 | PIO0_25 | GPIO with FC4/FC6 CTS/SDA/SSEL0; CTimer0 capture input 2 |
| F2 | PIO0_23 | GPIO with FC1 I2C SCL in ISP mode; CTimer0 capture input 0 |
| G2 | PIO0_22 | GPIO with CLKIN input; FC0 RXD/SDA/MOSI; CTimer3 match output 3 |
| A3 | PIO1_5 / ADC0_8 | ADC input channel 8; PDM1_DATA input; FC3 TXD/SCL/MISO |
| B3 | PIO1_3 / ADC0_6 | ADC input channel 6; FC7 SPI SSEL2; SCT0 PWM output 6; USB_UP_LED indicator |
| C3 | PIO1_0 / ADC0_3 | ADC input channel 3; PDM0_DATA input; FC2 RTS/SCL/SSEL1 |
| D3 | PIO0_29 / ADC0_0 | ADC input channel 0; FC1 RXD/SDA/MOSI; SCT0 PWM output 2 |
| E3 | PIO0_21 | GPIO with CLKOUT; FC0 TXD/SCL/MISO; CTimer3 match output 0 |
| F3 | PIO0_20 / TMS | GPIO with TMS in boundary scan; FC5 RXD/SDA/MOSI; CTimer3 capture input 0 |
| G3 | PIO0_19 / TDI | GPIO with TDI in boundary scan; FC5 SCK; SCT0 PWM output 1 |
| A4 | SWDIO / PIO0_17 | Serial Wire Debug I/O (default after boot); FC3 SSEL3; CTimer3 match output 2 |
| B4 | SWCLK / PIO0_16 | Serial Wire Clock (default after boot); FC3 SSEL2; CTimer3 match output 1 |
| C4 | PIO0_15 / TDO | GPIO with TDO in boundary scan; FC3 RTS/SCL/SSEL1; CTimer2 match output 2 |
| D4 | VDDA | Analog power supply (1.62–3.6 V), separate from digital VDD for ADC noise immunity |
| E4 | VREFP | Positive reference voltage input for ADC (tied to VDDA or external precision source) |
| F4 | VREFN | Negative reference voltage input for ADC (tied to VSSA or external source) |
| G4 | PIO0_18 / TRST | GPIO with TRST in boundary scan; FC5 TXD/SCL/MISO; SCT0 PWM output 0 |
| A5 | PIO0_13 | GPIO with FC3 TXD/SCL/MISO in ISP mode; SCT0 PWM output 4; CTimer2 match output 0 |
| B5 | PIO0_12 | GPIO with FC3 RXD/SDA/MOSI in ISP mode; CTimer2 match output 3 |
| C5 | PIO0_11 | GPIO with FC3 SCK in ISP mode; FC6 RXD/SDA/MOSI/DATA; CTimer2 match output 1 |
| D5 | USB_DM | USB 2.0 full-speed differential data minus line; internal termination enabled in crystal-less mode |
| E5 | USB_DP | USB 2.0 full-speed differential data plus line; internal termination enabled in crystal-less mode |
| F5 | RESET | Active-low reset input; supports Power-On Reset (POR) and Brown-Out Detect (BOD) assertion |
| G5 | VSS | Digital ground; multiple VSS bumps ensure low-impedance return path for high-speed signals |
| A6 | PIO0_0 | GPIO with FC0 RXD/SDA/MOSI in ISP mode; CTimer0 capture input 0; SCT0 PWM output 3 |
| B6 | PIO0_1 | GPIO with FC0 TXD/SCL/MISO in ISP mode; CTimer0 capture input 1; SCT0 PWM output 1 |
| C6 | PIO0_5 | GPIO with FC6 RXD/SDA/MOSI/DATA; SCT0 PWM output 6; CTimer0 match output 0 |
| D6 | PIO0_6 | GPIO with FC6 TXD/SCL/MISO/WS; CTimer0 match output 1; UTICK_CAP0 input |
| E6 | PIO0_7 | GPIO with FC6 SCK; SCT0 PWM output 0; CTimer0 match output 2 |
| F6 | PIO0_14 / TCK | GPIO with TCK in boundary scan; FC3 CTS/SDA/SSEL0; SCT0 PWM output 5 |
| G6 | PIO0_15 / TDO | GPIO with TDO in boundary scan; FC3 RTS/SCL/SSEL1; CTimer2 match output 2 |
| A7 | RTCXIN | 32.768 kHz crystal input for RTC oscillator; supports low-power timekeeping in deep power-down |
| B7 | RTCXOUT | 32.768 kHz crystal output for RTC oscillator; drives external crystal load capacitance |
| C7 | PIO0_4 | GPIO with FC0 SCK in ISP mode; FC3 SSEL2; CTimer0 capture input 2; boot source select |
| D7 | PIO0_6 | GPIO with FC6 TXD/SCL/MISO/WS; CTimer0 match output 1; UTICK_CAP0 input |
| E7 | PIO0_9 | GPIO with FC2 TXD/SCL/MISO; SCT0 PWM output 2; CTimer3 capture input 0 |
| F7 | PIO0_12 | GPIO with FC3 RXD/SDA/MOSI in ISP mode; CTimer2 match output 3 |
| G7 | PIO0_13 | GPIO with FC3 TXD/SCL/MISO in ISP mode; SCT0 PWM output 4; CTimer2 match output 0 |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core asymmetric processing | Offloads real-time audio preprocessing (M0+) from application logic (M4), enabling deterministic latency and reduced firmware complexity |
| Crystal-less USB 2.0 FS | Eliminates external 12 MHz crystal and associated capacitors, reducing BOM cost and PCB area while maintaining ±0.25 % USB timing tolerance |
| Integrated DMIC subsystem | Hardware-accelerated PDM-to-PCM conversion with decimation, FIFO buffering, and voice activity detection-no CPU cycles required for raw microphone ingestion |
| Flexible Flexcomm interfaces | Eight software-configurable serial peripherals allow dynamic reassignment of USART/SPI/I2C/I2S functions without hardware changes or pin remapping |
| Multi-domain power management | Programmable PMU enables independent clock gating, voltage scaling, and sleep mode entry per peripheral cluster, extending battery life in portable devices |
| Robust analog subsystem | 12-bit ADC with 5.0 MS/s throughput, 12-channel mux, dual conversion sequences, and integrated temperature sensor enable high-fidelity sensor fusion without external signal conditioning |
Applications
| Voice-Controlled Edge Node | Industrial Sensor Hub |
|---|---|
Use Scenario: Compact smart speaker endpoint with far-field PDM microphones, local wake-word detection, and USB-C audio streaming to host PC. IC Role / Device Role / Timing Role: Primary MCU executing dual-core firmware: M0+ handles PDM sampling, decimation, and VAD; M4 runs neural inference and USB CDC audio stack. Use Value: Crystal-less USB eliminates timing component; DMIC subsystem reduces M0+ CPU load by >70 % vs. bit-banged PDM; WLCSP49 enables <8 mm² PCB footprint. | Use Scenario: DIN-rail mounted environmental monitor aggregating temperature, humidity, and vibration data from multiple sensors, transmitting via USB to SCADA system. IC Role / Device Role / Timing Role: Central acquisition controller managing 12-channel ADC sampling, I2C sensor reads, RTC timestamping, and USB bulk transfers at 100 Hz update rate. Use Value: 192 KB SRAM buffers 10+ seconds of sensor data; 5.0 MS/s ADC oversamples for noise rejection; −40 °C to +105 °C rating ensures reliability in uncontrolled enclosures. |
| USB-C Connected Medical Device | Low-Power IoT Gateway |
Use Scenario: Portable ECG patch with analog front-end, real-time QRS detection, and USB-powered firmware updates and data export. IC Role / Device Role / Timing Role: Safety-critical signal processor: M4 runs FDA-compliant QRS algorithm and USB DFU bootloader; M0+ manages ADC triggers and GPIO safety interlocks. Use Value: Dual-core isolation prevents USB stack faults from compromising medical algorithms; MPUs enforce memory boundaries; crystal-less USB simplifies regulatory EMC testing. | Use Scenario: Battery-powered LoRaWAN gateway collecting BLE sensor data, performing local aggregation, and uploading summaries via USB to cloud gateway. IC Role / Device Role / Timing Role: Power-optimized coordinator: M0+ wakes periodically to scan BLE, M4 processes payloads and schedules USB transfers only during charging events. Use Value: Deep power-down mode draws <2 µA; Micro-Tick Timer enables sub-millisecond wake intervals; 256 KB flash stores dual-image bootloader for field updates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core ARM microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC54114J256UK49Z | Same package and core configuration, but adds USB High-Speed (HS) capability and second USB port | Required for applications needing simultaneous FS and HS USB connectivity or dual-device enumeration | Select when USB bandwidth exceeds 12 Mbps or dual-port topology is mandatory |
| LPC55S16JBD64K | Single Cortex-M33 core (150 MHz) with TrustZone, 256 KB flash, 192 KB SRAM, no M0+ coprocessor, LQFP64 package | Suitable for security-critical applications requiring hardware root-of-trust, but lacks asymmetric audio preprocessing offload | Select when secure boot, cryptographic acceleration, or larger I/O count (64-pin) outweighs need for dual-core audio pipeline |
Compared with LPC54114J256UK49Z, the LPC54113J256UK49Z omits USB HS and second port-reducing cost and power-but retains identical dual-core audio processing capability; versus LPC55S16JBD64K, it trades TrustZone security for deterministic real-time partitioning between M4 and M0+ cores in a smaller WLCSP footprint.
Availability
LPC54113J256UK49Z is available at Aetrix Electronics and suitable for voice-controlled edge nodes, industrial sensor hubs, and USB-C connected medical devices requiring stable component supply, long-term lifecycle support, and wafer-level packaging for space-constrained designs.
Supply support for LPC54113J256UK49Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The LPC5411x product line delivers dual-core ARM microcontrollers optimized for ultra-low-power, audio-centric embedded systems-designed to simplify voice interface integration, reduce external component count, and accelerate time-to-market for intelligent edge devices.
FAQ
What is the maximum operating frequency of the LPC54113J256UK49Z?
The LPC54113J256UK49Z supports a maximum CPU frequency of 150 MHz for both the ARM Cortex-M4 and Cortex-M0+ cores. This frequency is achieved using the system PLL driven by the internal 12 MHz Free Running Oscillator (FRO), eliminating the need for an external high-frequency crystal while maintaining timing accuracy within ±1 % over voltage and temperature.
Does the LPC54113J256UK49Z support crystal-less USB operation?
Yes, the LPC54113J256UK49Z supports crystal-less USB 2.0 full-speed device operation using its internal FRO and software library (documented in Technical Note TN00031). This eliminates the need for an external 12 MHz crystal and associated load capacitors, reducing BOM cost and PCB area while meeting USB timing tolerance requirements.
How many ADC channels does the LPC54113J256UK49Z have, and what is its maximum sample rate?
The LPC54113J256UK49Z integrates a 12-bit ADC with 12 input channels and supports a maximum sample rate of 5.0 million samples per second. It provides two independent conversion sequences and connects to an on-chip temperature sensor, enabling high-throughput sensor fusion without external ADC components.
What package type is used for the LPC54113J256UK49Z?
The LPC54113J256UK49Z uses a WLCSP49 (Wafer-Level Chip-Scale Package) with 49 bumps arranged in a 7×7 array, measuring 3.436 × 3.436 × 0.525 mm and featuring a 0.4 mm bump pitch. This ultra-compact package is optimized for space-constrained portable and wearable applications.
Can the LPC54113J256UK49Z operate across extended temperature ranges?
Yes, the LPC54113J256UK49Z is rated for operation from −40 °C to +105 °C, making it suitable for industrial, automotive, and outdoor environments where thermal robustness is critical. Its internal oscillators-including the 12 MHz FRO trimmed to ±1 % accuracy-are specified across this full range.
LPC54113J256UK49Z Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 49-UFBGA, WLCSP
- Series:
- LPC54100
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M4
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- I2C, SPI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, POR, PWM, WDT
- Number of I/O:
- 39
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 192K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.62V ~ 3.6V
- Data Converters:
- A/D 12x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC54113J256UK49Z FAQ
1.How can I place an order for LPC54113J256UK49Z through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC54113J256UK49Z on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC54113J256UK49Z reliable?
The price and inventory of LPC54113J256UK49Z are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC54113J256UK49Z is usually 5 days.
3.What payment methods are accepted for LPC54113J256UK49Z?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC54113J256UK49Z transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC54113J256UK49Z?
LPC54113J256UK49Z orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC54113J256UK49Z order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC54113J256UK49Z?
For technical support, including LPC54113J256UK49Z datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC54113J256UK49Z requirements.
6.How does Aetrix verify that LPC54113J256UK49Z is sourced from the original manufacturer or authorized distributors?
All LPC54113J256UK49Z products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC54113J256UK49Z meets industry standards.
7.What is the process for return or replacement of LPC54113J256UK49Z?
All LPC54113J256UK49Z units undergo pre-shipment inspection (PSI). If there is an issue with LPC54113J256UK49Z, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC54113J256UK49Z part is unused and in its original packaging.
Return procedure for LPC54113J256UK49Z:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC54113J256UK49Z Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

