My Inquiry
My Account
NXP Semiconductors LPC5502JBD64K
- Part No.:
- LPC5502JBD64K
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 64-TQFP Exposed Pad
- Datasheet:
-
LPC5502JBD64K.pdf
- Description:
- IC MCU 32BIT 64KB FLASH 64TQFP
- Quantity:
- Payment:
- Shipping:
Inventory:800
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC5502JBD64 from NXP Semiconductors is a 32-bit ARM Cortex-M33 microcontroller designed for secure, low-power embedded control applications. It operates at up to 96 MHz, integrates 64 KB flash and 48 KB SRAM, supports CAN 2.0 (not CAN FD), and includes a 16-bit 2.0 Msamples/sec ADC with nine input channels - deployed in industrial sensor nodes requiring deterministic real-time response and firmware integrity.
For engineers reviewing the LPC5502JBD64 datasheet, LPC5502JBD64 pinout, LPC5502JBD64 application, or LPC5502JBD64 equivalent, key selection criteria include its HTQFP64 package with 45 GPIOs, TrustZone®-enabled security architecture without PUF or CASPER, PRINCE flash encryption support, and compatibility with NXP's MCUXpresso SDK for secure boot implementation.
Technical Context
The LPC5502JBD64 implements ARMv8-M architecture with TrustZone® for hardware-enforced memory isolation, but omits the CASPER crypto co-processor and Physical Unclonable Function (PUF) found in S-series variants. Its security stack relies on PRINCE-based flash encryption, SHA/AES hardware acceleration, and RSA-2048/4096 secure boot verification using x.509 certificates.
It features eight Flexcomm interfaces (UART/I2C/SPI/I2S configurable per channel), five 32-bit general-purpose timers, an SCTimer/PWM with 10 outputs, and a dedicated CAN 2.0 controller - all accessible via AHB/APB interconnect with DMA0/DMA1 controllers supporting concurrent peripheral transfers without CPU intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M33 @ 96 MHz with FPU, MPU, and TrustZone® for secure partitioning |
| Memory | 64 KB on-chip flash (512-byte page erase) + 48 KB SRAM (16 KB code bus + 32 KB system bus) |
| Analog Peripherals | 16-bit 2.0 Msamples/sec ADC with 9 channels; integrated temperature sensor and comparator |
| Serial Interfaces | 8 Flexcomm modules (configurable as USART/I2C/SPI/I2S) + 1 HS SPI + CAN 2.0 controller |
| Security Features | PRINCE flash encryption/decryption, SHA-256/AES-256 engines, RSA-2048/4096 secure boot, no PUF or CASPER |
| Package & Temp | HTQFP64 (10 × 10 × 0.5 mm), −40 °C to +105 °C operating range |
| Power Supply | Single 1.8 V–3.6 V supply with internal DC-DC converter and multiple low-power modes |
Pinout & Package
Package: HTQFP64 (plastic low-profile quad flat package, 64 leads, 10 × 10 × 0.5 mm body, SOT 855-5).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PIO0_0 / ACMP0_A | GPIO / Analog Comparator Input A | Dual-role pin usable as digital I/O or comparator input when analog mode enabled; default reset state is high-impedance |
| PIO0_2 / TRST | JTAG Test Reset Input | Hardware-controlled boundary scan reset; also serves as general GPIO or Flexcomm 3 clock in normal operation |
| PIO0_3 / TCK | JTAG Test Clock Input | Synchronizes JTAG interface; multiplexed with Flexcomm 3 data I/O and CTimer0 match output |
| PIO0_4 / TMS | JTAG Test Mode Select | Selects JTAG instruction register; also functions as CAN0 receiver input or Flexcomm 4 clock |
| PIO0_5 / TDI | JTAG Test Data Input | Loads instructions/data into JTAG DR/IR; boot source selection determined by pin state at reset |
| PIO0_6 / TDO | JTAG Test Data Output | Serial output of JTAG shift register; also used for Flexcomm 3 clock or CTimer4 match output |
| XTAL32K_P / XTAL32K_N | 32.768 kHz Crystal Interface | Differential crystal input for RTC domain; enables wake-up from deep power-down with 1 ms resolution |
| VDD / VSS | Power Supply / Ground | Multiple VDD pins (pins 5, 6, 8, 12, 16, 27, 43) ensure stable core voltage; exposed pad must connect to VSS |
Key Features
| Feature | Design Value |
|---|---|
| TrustZone® Security | Hardware-isolated secure/non-secure memory regions enabling certified secure boot and runtime IP protection |
| PRINCE Flash Encryption | Real-time AES-128 encryption/decryption of flash reads/writes to prevent firmware extraction or tampering |
| Flexible Serial Connectivity | Eight software-configurable Flexcomm interfaces support mixed UART/I2C/SPI/I2S protocols on shared pins |
| High-Speed Analog Capture | 16-bit ADC sampling at 2.0 Msamples/sec with simultaneous dual-channel conversion capability |
| Deterministic Timing Control | SCTimer/PWM with 10 outputs, 16 match/capture registers, and programmable state machine logic for complex waveform generation |
Applications
| Industrial Sensor Node | Secure Gateway Controller |
|---|---|
Use Scenario: Remote environmental monitoring unit collecting temperature, pressure, and vibration data in oil/gas field equipment. IC Role / Device Role / Timing Role: Main MCU executing sensor fusion algorithms, managing CAN 2.0 communication with field devices, and enforcing secure OTA firmware updates. Use Value: PRINCE-encrypted flash prevents unauthorized firmware modification; 2.0 Msamples/sec ADC captures transient mechanical events with sub-microsecond timing resolution. | Use Scenario: Edge gateway aggregating data from legacy CAN 2.0 subsystems before forwarding to cloud via Ethernet/Wi-Fi. IC Role / Device Role / Timing Role: Protocol translation hub with deterministic CAN message scheduling, secure boot validation, and cryptographic signing of telemetry payloads. Use Value: TrustZone® isolates secure boot loader from application firmware; SHA/AES hardware accelerators enable real-time payload signing without CPU overhead. |
| Smart Energy Meter | Medical Diagnostic Interface |
Use Scenario: UL-certified electricity meter performing harmonic analysis and tamper detection in residential utility infrastructure. IC Role / Device Role / Timing Role: Real-time signal processor capturing voltage/current waveforms via ADC, calculating RMS/harmonics, and logging events to encrypted flash. Use Value: 16-bit ADC with simultaneous dual-channel sampling ensures phase-aligned acquisition; 45 GPIOs support metrology sensor interfacing and anti-tamper switch monitoring. | Use Scenario: Portable ultrasound probe interface module converting analog transducer signals to digital streams for host processing. IC Role / Device Role / Timing Role: High-fidelity analog front-end controller synchronizing ADC sampling, generating precise timing triggers, and buffering data via DMA to external memory. Use Value: SCTimer/PWM generates exact ultrasonic pulse sequences; 2.0 Msamples/sec ADC resolves fine-grained tissue echogenicity without undersampling artifacts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC5504JBD64 | 128 KB flash, 80 KB SRAM, same HTQFP64 package, identical peripheral set except higher memory capacity | Supports larger firmware images and more complex RTOS workloads; retains CAN 2.0 and PRINCE but no PUF/CASPER | Select when firmware size exceeds 64 KB or additional RAM is required for buffer-intensive tasks |
| LPC55S02JBD64 | Same memory (64 KB flash / 48 KB SRAM), adds CASPER crypto co-processor and PUF for enhanced asymmetric cryptography | Enables ECC-based device authentication and key derivation unsuitable for LPC5502JBD64's hardware-limited security stack | Choose when Elliptic Curve Cryptography (ECC) acceleration or silicon-rooted key generation is mandatory |
Compared with LPC5502JBD64, LPC5504JBD64 offers scalable memory headroom while maintaining identical security and timing capabilities, whereas LPC55S02JBD64 trades memory parity for dedicated crypto acceleration - making LPC5502JBD64 optimal for cost-sensitive, memory-constrained secure control where ECC is not required.
Availability
LPC5502JBD64 is available at Aetrix Electronics and suitable for industrial sensor nodes, secure gateways, smart energy meters, and medical diagnostic interfaces requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for LPC5502JBD64 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with over 40 years of microcontroller innovation.
The LPC5500 series targets cost-optimized, security-aware embedded control applications - delivering TrustZone®-enabled isolation, PRINCE flash encryption, and deterministic real-time peripherals without premium crypto accelerators.
FAQ
Does LPC5502JBD64 support CAN FD?
No, LPC5502JBD64 implements CAN 2.0 only. Unlike the LPC55S0x variants, it lacks the CAN FD controller and associated DMA support. Its CAN peripheral operates at up to 1 Mbps with standard 11-bit identifiers and does not support the extended data length or bit-rate switching features of CAN FD. This distinction is explicitly documented in Table 2 of the datasheet under the "CAN FD" column, which lists "CAN2.0" for LPC5502JBD64.
What security features are included in LPC5502JBD64?
LPC5502JBD64 includes ARM TrustZone® for memory isolation, PRINCE flash encryption/decryption, SHA-256 and AES-256 hardware engines, RSA-2048/4096 secure boot verification, and a Code Watchdog for runtime flow integrity. It does not include the CASPER crypto co-processor or Physical Unclonable Function (PUF) - both are exclusive to the "S"-suffix variants like LPC55S02JBD64.
Which development tools support LPC5502JBD64?
LPC5502JBD64 is fully supported by NXP's MCUXpresso IDE and SDK, including drivers for PRINCE, SCTimer/PWM, Flexcomm interfaces, and secure boot configuration utilities. It is compatible with LPC-Link2 and J-Link debug probes via SWD, and reference designs such as the LPCXpresso55S06 board can be adapted for evaluation using appropriate pin mapping and memory configuration.
What is the maximum ADC sampling rate of LPC5502JBD64?
The LPC5502JBD64 integrates a 16-bit ADC capable of 2.0 million samples per second (2.0 Msamples/sec). This rate applies to single-channel operation; simultaneous conversions on two channels within a differential pair maintain full resolution and timing alignment, enabling accurate phase-sensitive measurements in motor control or power quality monitoring.
Is LPC5502JBD64 pin-compatible with other LPC55xx devices in HTQFP64?
Yes, LPC5502JBD64 shares identical pinout and package (HTQFP64, SOT 855-5) with LPC5504JBD64, LPC5506JBD64, and LPC55S0xJBD64 variants. All share the same 64-pin assignment, power/ground distribution, and peripheral pin mappings - allowing direct PCB reuse across memory- and feature-tiered variants, provided firmware accounts for differing flash/SRAM sizes and enabled security blocks.
LPC5502JBD64K Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 64-TQFP Exposed Pad
- Series:
- LPC550x
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit Single-Core
- Speed:
- 96MHz
- Connectivity:
- CAN FD, Flexcomm, I2C, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, POR, PWM, RNG, WDT
- Number of I/O:
- 45
- Program Memory Size:
- 64KB (64K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 48K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 9x16b SAR
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC5502JBD64K FAQ
1.How can I place an order for LPC5502JBD64K through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC5502JBD64K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC5502JBD64K reliable?
The price and inventory of LPC5502JBD64K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC5502JBD64K is usually 5 days.
3.What payment methods are accepted for LPC5502JBD64K?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC5502JBD64K transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC5502JBD64K?
LPC5502JBD64K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC5502JBD64K order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC5502JBD64K?
For technical support, including LPC5502JBD64K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC5502JBD64K requirements.
6.How does Aetrix verify that LPC5502JBD64K is sourced from the original manufacturer or authorized distributors?
All LPC5502JBD64K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC5502JBD64K meets industry standards.
7.What is the process for return or replacement of LPC5502JBD64K?
All LPC5502JBD64K units undergo pre-shipment inspection (PSI). If there is an issue with LPC5502JBD64K, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC5502JBD64K part is unused and in its original packaging.
Return procedure for LPC5502JBD64K:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC5502JBD64K Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
