NXP Semiconductors LPC5502JBD64Y
- Part No.:
- LPC5502JBD64Y
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 64-TQFP Exposed Pad
- Datasheet:
-
LPC5502JBD64Y.pdf
- Description:
- IC MCU 32BIT 64KB FLASH 64TQFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,470
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC5502JBD64Y from NXP Semiconductors is a 32-bit ARM Cortex-M33 microcontroller designed for secure embedded control applications. It operates at up to 96 MHz, integrates 64 KB flash and 48 KB SRAM, supports CAN 2.0 (not CAN FD), and includes a 16-bit 2.0 Msamples/sec ADC with nine input channels. It targets industrial sensor nodes requiring deterministic real-time response and firmware integrity.
For engineers reviewing the LPC5502JBD64Y datasheet, LPC5502JBD64Y pinout, LPC5502JBD64Y application, or LPC5502JBD64Y equivalent, key selection criteria include its HTQFP64 package with 45 GPIOs, TrustZone®-enabled security architecture without PUF or CASPER, PRINCE flash encryption support, and compatibility with NXP's MCUXpresso SDK for secure boot implementation.
Technical Context
The LPC5502JBD64Y implements ARMv8-M architecture with TrustZone® for hardware-enforced memory isolation, but omits PUF, CASPER, and Secure Boot cryptographic acceleration blocks present in S-series variants. Its security model relies on PRINCE-based flash encryption and software-managed AES/SHA via Hash-AES module.
It features eight Flexcomm interfaces (UART/I2C/SPI/I2S configurable per channel), five 32-bit general-purpose timers, one SCTimer/PWM, and a dedicated CAN 2.0 controller - distinct from CAN FD found in LPC55S0x derivatives. The 16-bit ADC supports simultaneous sampling on differential pairs at up to 2.0 Msamples/sec.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M33 @ 96 MHz with TrustZone® and FPU - enables secure RTOS partitioning and DSP-intensive signal processing. |
| Memory | 64 KB flash / 48 KB SRAM - sufficient for compact firmware with encrypted OTA update capability via PRINCE. |
| Analog | 16-bit ADC, 2.0 Msamples/sec, 9 channels - supports high-fidelity sensor acquisition in motor control or power monitoring. |
| Serial Interfaces | 8 Flexcomm + 1 HS SPI + CAN 2.0 - provides flexible peripheral bridging without CAN FD data-rate extension. |
| Security | PRINCE flash encryption, Hash-AES engine, no PUF/CASPER - enables asset protection but requires external key management for asymmetric crypto. |
| Package | HTQFP64 (10 × 10 × 0.5 mm) - standard QFP footprint with exposed thermal pad for industrial thermal reliability. |
| Operating Range | −40 °C to +105 °C, 1.8–3.6 V supply - qualified for extended-temperature industrial and automotive under-hood environments. |
Pinout & Package
HTQFP64 package: plastic low-profile quad flat package with 64 leads, 10 × 10 × 0.5 mm body, exposed thermal pad connected to VSS.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PIO0_0/ACMP0_A | GPIO / Analog comparator input A | Configurable as digital I/O or comparator input when analog mode enabled; supports wake-up and secure GPIO functions. |
| PIO0_2/TRST | JTAG test reset / GPIO | Hardware TRST in boundary scan mode; default pull-down ensures safe debug initialization during power-on. |
| PIO0_3/TCK | JTAG clock input / GPIO | Primary debug clock path; must be driven externally for SWD/JTAG programming and trace synchronization. |
| PIO0_4/TMS | JTAG mode select / CAN0_RD | Dual-role pin: controls JTAG state machine or receives CAN 2.0 bus signals - not simultaneously active. |
| PIO0_5/TDI | JTAG data input / CAN0_TD | Boot source selector at reset: logic level determines ISP entry or flash execution - critical for field firmware recovery. |
| RESETN | Active-low reset input | Asynchronous reset assertion clears CPU, peripherals, and clocks; debounced externally for robust deep-power-down wake-up. |
| VDD / VDDA / VSSA | Power supply / analog reference | Separate analog/digital domains ensure ADC accuracy; VDDA must be filtered independently for <1 LSB noise performance. |
Key Features
| Feature | Design Value |
|---|---|
| TrustZone®-enabled Cortex-M33 | Hardware-isolated secure/non-secure worlds enable certified bootloader and firmware separation without software overhead. |
| PRINCE flash encryption | Real-time AES-128 encryption/decryption of flash reads/writes prevents unauthorized firmware extraction or tampering. |
| 8 Flexcomm interfaces | Software-configurable UART/I2C/SPI/I2S per interface - eliminates need for external protocol translators in multi-sensor gateways. |
| 16-bit 2.0 Msamples/sec ADC | Simultaneous sampling on differential pairs enables precise phase-current measurement in BLDC motor control. |
| 45 GPIO with secure attributes | Individual GPIOs can be assigned secure/non-secure access rights - enforces peripheral-level privilege boundaries. |
Applications
| Industrial Sensor Node | Smart Power Meter |
|---|---|
Use Scenario: Remote environmental monitoring with vibration, temperature, and humidity sensing, transmitting data over RS-485 and LoRaWAN. IC Role / Device Role / Timing Role: Central controller managing sensor acquisition, PRINCE-encrypted local logging, and secure firmware updates via CAN 2.0 or UART. Use Value: TrustZone® isolates sensor data collection from communication stack, preventing side-channel leakage during OTA updates. | Use Scenario: DIN-rail mounted electricity meter with harmonic analysis, tamper detection, and DLMS/COSEM protocol compliance. IC Role / Device Role / Timing Role: Real-time energy calculation engine interfacing with metrology ADC, isolated CAN 2.0 for utility backhaul, and secure boot validation. Use Value: 16-bit ADC sampling at 2.0 Msamples/sec enables accurate 50/60 Hz fundamental and harmonic reconstruction per IEC 62053. |
| Automotive Body Control Module | Secure Industrial PLC I/O Expander |
Use Scenario: Door module controlling window lift, mirror adjustment, and interior lighting with LIN and CAN 2.0 connectivity. IC Role / Device Role / Timing Role: Safety-aware MCU executing ASIL-B diagnostics, CAN 2.0 messaging, and PWM-driven motor control with watchdog supervision. Use Value: Windowed Watchdog Timer (WWDT) and Code Watchdog jointly verify instruction flow integrity across safety-critical routines. | Use Scenario: Modular I/O subsystem for programmable logic controllers, supporting analog inputs, digital outputs, and fieldbus bridging. IC Role / Device Role / Timing Role: Deterministic I/O processor with SCTimer/PWM for servo timing, PRINCE-protected configuration storage, and secure firmware loading. Use Value: SCTimer/PWM's 16 capture/match registers enable precise synchronization of distributed I/O cycles across multiple expansion modules. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC55S02JBD64 | Includes CASPER crypto co-processor, PUF, and full Secure Boot with RSA-2048/4096 - adds ~15% BOM cost and 3–5 ms boot latency. | Required for FIPS 140-3 Level 1 certification or DICE-compliant device identity generation. | Select when cryptographic key derivation, remote attestation, or anti-rollback enforcement is mandatory. |
| LPC5506JBD64 | Same package and pinout, but with 256 KB flash and 96 KB SRAM - no change to security feature set or peripheral count. | Suitable for larger firmware images with dual-bank OTA, complex GUI stacks, or extended diagnostic logging buffers. | Choose when memory headroom is needed without altering hardware design or security architecture. |
Compared with LPC5502JBD64Y, LPC55S02JBD64 adds hardware-accelerated asymmetric crypto and silicon-rooted key generation, while LPC5506JBD64 offers scalable memory for feature-rich firmware - both retain identical HTQFP64 layout and CAN 2.0 interface behavior.
Availability
LPC5502JBD64Y is available at Aetrix Electronics and suitable for industrial sensor nodes, smart power meters, automotive body control modules, and secure industrial PLC I/O expanders requiring stable component supply across extended temperature ranges.
Supply support for LPC5502JBD64Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with R&D centers across Europe, Asia, and North America.
The LPC5500 series targets cost-optimized, security-conscious embedded control applications where full cryptographic acceleration is unnecessary - emphasizing deterministic real-time performance, PRINCE-based firmware protection, and industrial-grade reliability.
FAQ
Does LPC5502JBD64Y support CAN FD?
No, LPC5502JBD64Y implements CAN 2.0 only. Unlike LPC55S0x variants, it lacks the CAN FD controller and associated DMA enhancements. Applications requiring CAN FD data rates up to 5 Mbit/s must use LPC55S02JBD64 or higher S-series derivatives instead of LPC5502JBD64Y.
What security features are included in LPC5502JBD64Y?
LPC5502JBD64Y includes ARM TrustZone®, PRINCE flash encryption, Hash-AES cryptographic engine, and secure GPIO functionality. It does not include PUF, CASPER co-processor, or hardware RSA acceleration - those features are exclusive to LPC55S0x models. Secure boot relies on software-managed SHA256/AES operations.
Is LPC5502JBD64Y pin-compatible with LPC55S02JBD64?
Yes, LPC5502JBD64Y and LPC55S02JBD64 share identical HTQFP64 pinout, electrical characteristics, and peripheral mapping. They differ only in internal feature enablement (e.g., CASPER, PUF, Secure Boot keys). PCB designs for one can host the other without layout changes, enabling late-stage security upgrades.
What is the maximum ADC sampling rate supported by LPC5502JBD64Y?
LPC5502JBD64Y supports a maximum ADC sampling rate of 2.0 Msamples/sec in single-channel mode. When configured for simultaneous conversion on differential pairs, effective throughput remains at 2.0 Msamples/sec across two channels, preserving timing correlation for motor current sensing or audio sampling.
Does LPC5502JBD64Y include a temperature sensor?
Yes, LPC5502JBD64Y integrates an on-die temperature sensor connected directly to the 16-bit ADC. It provides calibrated readings across −40 °C to +105 °C with ±2.5 °C accuracy, usable for thermal management in motor drives or ambient condition monitoring without external components.
LPC5502JBD64Y Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 64-TQFP Exposed Pad
- Series:
- LPC550x
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit Single-Core
- Speed:
- 96MHz
- Connectivity:
- CAN FD, Flexcomm, I2C, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, POR, PWM, RNG, WDT
- Number of I/O:
- 45
- Program Memory Size:
- 64KB (64K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 48K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 9x16b SAR
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC5502JBD64Y FAQ
1.How can I place an order for LPC5502JBD64Y through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC5502JBD64Y on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC5502JBD64Y reliable?
The price and inventory of LPC5502JBD64Y are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC5502JBD64Y is usually 5 days.
3.What payment methods are accepted for LPC5502JBD64Y?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC5502JBD64Y transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC5502JBD64Y?
LPC5502JBD64Y orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC5502JBD64Y order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC5502JBD64Y?
For technical support, including LPC5502JBD64Y datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC5502JBD64Y requirements.
6.How does Aetrix verify that LPC5502JBD64Y is sourced from the original manufacturer or authorized distributors?
All LPC5502JBD64Y products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC5502JBD64Y meets industry standards.
7.What is the process for return or replacement of LPC5502JBD64Y?
All LPC5502JBD64Y units undergo pre-shipment inspection (PSI). If there is an issue with LPC5502JBD64Y, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC5502JBD64Y part is unused and in its original packaging.
Return procedure for LPC5502JBD64Y:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC5502JBD64Y Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

