NXP Semiconductors LPC5502JHI48EL
- Part No.:
- LPC5502JHI48EL
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
LPC5502JHI48EL.pdf
- Description:
- IC MCU 32BIT 64KB FLASH 48VFQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LPC5502JHI48EL from NXP Semiconductors is a 32-bit ARM Cortex-M33 microcontroller designed for secure, low-power embedded control in industrial and IoT edge nodes. It operates at up to 96 MHz, integrates 64 KB flash and 48 KB SRAM, features CAN 2.0 (not CAN FD), and includes a 16-bit 2.0 Msamples/sec ADC with seven analog input channels - deployed in smart sensor hubs requiring deterministic real-time response and firmware integrity.
For engineers reviewing the LPC5502JHI48EL datasheet, LPC5502JHI48EL pinout, LPC5502JHI48EL application, or LPC5502JHI48EL equivalent, key selection criteria include its HVQFN48 package footprint, TrustZone®-enabled security architecture without PUF or CASPER, PRINCE flash encryption support, and compatibility with NXP's MCUXpresso SDK for secure boot implementation and peripheral configuration.
Technical Context
The LPC5502JHI48EL implements ARMv8-M architecture with TrustZone® for hardware-enforced memory isolation, enabling secure firmware execution alongside non-secure application code. Its clock system combines internal FROs (96 MHz, 32 kHz, 1 MHz) with PLLs and external crystal support (16–32 MHz, 32.768 kHz), delivering precise timing across operating modes from active to deep power-down.
Peripheral integration centers on seven Flexcomm interfaces (UART/I2C/SPI/I2S), five 32-bit general-purpose timers, one SCTimer/PWM with 10 outputs, PLU for logic offload, and a dual-channel simultaneous-capable ADC - all accessible via AHB/APB bridges and configurable through IOCON registers without requiring external glue logic.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M33 @ 96 MHz - delivers deterministic real-time control with DSP instructions and FPU for sensor fusion math. |
| Memory | 64 KB flash / 48 KB SRAM - sufficient for compact RTOS-based firmware with encrypted OTA update capability via PRINCE. |
| Analog Peripherals | 16-bit 2.0 Msamples/sec ADC (7 ch) + comparator + temp sensor - enables high-resolution signal acquisition in motor control or environmental monitoring. |
| Serial Interfaces | 7 Flexcomm units (configurable as UART/I2C/SPI/I2S) + CAN 2.0 - supports multi-protocol fieldbus connectivity without external transceivers. |
| Security Features | TrustZone®, PRINCE, HASH-AES, RNG, Secure Boot (RSA-2048/4096), Code Watchdog - meets TBSA compliance for firmware integrity and anti-rollback protection. |
| Package | HVQFN48 (7 × 7 × 0.85 mm) - thermal-enhanced, leadless footprint optimized for space-constrained industrial PCBs with exposed pad for thermal dissipation. |
| Operating Range | −40 °C to +105 °C, 1.8–3.6 V supply - qualified for extended-temperature industrial environments with integrated DC-DC converter. |
Pinout & Package
HVQFN48 package with 48 terminals, 7 mm × 7 mm body, 0.85 mm height, and exposed thermal pad connected to VSS. Pin numbering follows standard counter-clockwise layout starting from top-left corner (pin 1 = PIO1_0/ADC0_11).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PIO1_0 / ADC0_11 | Analog input / GPIO | Primary ADC channel 11 input; default GPIO function unless ANAMODE enabled in IOCON register. |
| PIO0_2 / TRST | JTAG test reset | Hardware-controlled boundary scan reset; internal pull-down enabled at reset to ensure stable debug initialization. |
| PIO0_3 / TCK | JTAG clock input | Test clock for IEEE 1149.1 boundary scan; not usable for debug during normal operation when JTAG is disabled. |
| PIO0_4 / TMS | JTAG mode select | Selects JTAG state machine transitions; also serves as CAN0 receiver input when digital functions are configured. |
| PIO0_5 / TDI | JTAG data input | Boot source selector - pin state at reset determines whether ROM bootloader loads from flash or enters ISP mode. |
| PIO0_6 / TDO | JTAG data output | Boundary scan output only; not available for SWD or functional I/O until JTAG mode is exited. |
| XTAL32M_P / XTAL32M_N | High-speed crystal oscillator | Differential 16–32 MHz crystal interface with embedded capacitor banks for CL tuning - eliminates external load capacitors. |
| XTAL32K_P / XTAL32K_N | RTC crystal oscillator | 32.768 kHz crystal input for RTC and low-power wake-up timer - runs in always-on domain during deep power-down. |
| VDD / VDDA / VSSA | Power domains | Separate analog/digital supplies enable noise isolation for ADC accuracy; VDDA must be ≥ VDD for proper analog operation. |
| RESETN | Active-low reset | Asynchronous external reset input; triggers full chip reset including security state machines and memory controllers. |
Key Features
| Feature | Design Value |
|---|---|
| PRINCE Flash Encryption | Real-time AES-128 encryption/decryption of on-chip flash reads/writes - protects firmware IP without performance penalty or external crypto IC. |
| Flexcomm Interface Flexibility | Seven software-configurable serial peripherals per device - reduces BOM count by eliminating dedicated UART/SPI/I2C ICs in multi-interface designs. |
| SCTimer/PWM Precision | 10 output channels with 16 match/capture registers and state-machine logic - enables complex waveform generation for motor gate drive or lighting control. |
| Secure Boot Enforcement | RSA-2048/4096 signature verification using x.509 certificates and up to four revocable Root-of-Trust keys - prevents unauthorized firmware execution at power-on. |
| Low-Power Wake-Up Sources | RTC alarm, Micro-Tick Timer, GPIO interrupts, and CAN activity - allows sub-μA deep-sleep current while maintaining responsive event-driven wake-up latency. |
Applications
| Industrial Sensor Node | Smart Building Controller |
|---|---|
Use Scenario: Wireless temperature/humidity node with local edge analytics and CAN bus backhaul to gateway. IC Role / Device Role / Timing Role: Main controller executing sensor fusion algorithms, managing PRINCE-encrypted OTA updates, and driving CAN 2.0 communication stack. Use Value: 64 KB flash accommodates secure bootloader + application + crypto libraries; 7 ADC channels acquire multi-sensor data simultaneously at 2 Msps for real-time filtering. | Use Scenario: HVAC zone controller interfacing with thermostats, actuators, and building management system via CAN. IC Role / Device Role / Timing Role: Real-time deterministic scheduler coordinating PWM fan control, temperature regulation, and fault-safe CAN messaging. Use Value: SCTimer/PWM generates precise variable-frequency drive signals; TrustZone® isolates safety-critical HVAC logic from non-critical UI tasks. |
| Energy Metering Endpoint | Secure Firmware Update Hub |
Use Scenario: DIN-rail mounted electricity meter with tamper detection, pulse counting, and encrypted data logging. IC Role / Device Role / Timing Role: High-accuracy ADC front-end processor with comparator-based overvoltage detection and secure flash storage. Use Value: 16-bit ADC achieves >90 dB SNR for Class 0.5 metering; PRINCE ensures firmware integrity during remote updates over constrained LPWAN links. | Use Scenario: Field-deployed gateway that validates and distributes signed firmware images to downstream edge devices. IC Role / Device Role / Timing Role: Cryptographic co-processor offloading RSA signature verification and AES decryption for SB2-format images. Use Value: HASH-AES engine accelerates image validation; secure GPIO pins isolate trusted update path from untrusted network interfaces. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC5504JHI48 | 128 KB flash / 80 KB SRAM; same HVQFN48 package and peripheral set - no CASPER/PUF but retains PRINCE and TrustZone®. | Supports larger firmware images and more complex RTOS configurations; suitable where extended secure storage or additional DMA channels are required. | Select when firmware size exceeds 64 KB or when additional SRAM is needed for cryptographic buffers or network stacks. |
| LPC55S02JHI48 | 64 KB flash / 48 KB SRAM; adds CASPER crypto accelerator and PUF - identical package and pinout to LPC5502JHI48. | Enables ECC-based key generation and hardware-accelerated asymmetric crypto; required for DICE-compliant device identity provisioning. | Choose when Elliptic Curve Cryptography or silicon-unique key derivation is mandatory for device attestation or zero-touch provisioning. |
Compared with LPC5502JHI48, LPC5504JHI48 provides scalable memory headroom for evolving firmware, while LPC55S02JHI48 adds hardware crypto acceleration for advanced identity and key management - both maintain identical HVQFN48 mechanical fit and CAN 2.0 interface compatibility.
Availability
LPC5502JHI48EL is available at Aetrix Electronics and suitable for industrial sensor nodes, smart building controllers, energy metering endpoints, and secure firmware update hubs requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for LPC5502JHI48EL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT markets, with headquarters in Eindhoven, Netherlands.
The LPC5500 series targets cost-optimized, security-conscious embedded applications - delivering ARM Cortex-M33 performance with hardware-enforced trust, low-power operation, and flexible peripheral routing for rapid development of certified edge devices.
FAQ
What is the maximum operating frequency of the LPC5502JHI48EL?
The LPC5502JHI48EL operates at a maximum CPU frequency of 96 MHz using its internal 96 MHz Free Running Oscillator (FRO) or PLL-derived clocks. This frequency is achievable across the full −40 °C to +105 °C temperature range and 1.8–3.6 V supply voltage, with FRO trimming ensuring ±1% accuracy at 25 °C and ±2% over the full range.
Does the LPC5502JHI48EL support CAN FD or only classical CAN?
The LPC5502JHI48EL supports only CAN 2.0 (Classical CAN) - not CAN FD. This is confirmed in Table 2 of the datasheet, which lists "CAN2.0" under the CAN FD column for all LPC550x variants, distinguishing them from LPC55S0x parts that explicitly list "CAN FD". The CAN module is fully compatible with ISO 11898-1 and supports bit rates up to 1 Mbps.
How many ADC channels does the LPC5502JHI48EL provide, and what is its sampling rate?
The LPC5502JHI48EL integrates a 16-bit ADC with seven single-ended input channels (or three differential pairs plus one single-ended), supporting simultaneous conversions on two channels within a pair. Its maximum sampling rate is 2.0 Msamples/sec, enabled by dedicated hardware triggers and DMA support - sufficient for high-fidelity sensor data acquisition in motor control or audio preprocessing.
Is the LPC5502JHI48EL pin-compatible with other LPC55xx HVQFN48 variants?
Yes, the LPC5502JHI48EL is pin-compatible with all other HVQFN48-packaged LPC55xx devices, including LPC5504JHI48, LPC5506JHI48, LPC55S02JHI48, and LPC55S04JHI48. All share identical pin counts, physical dimensions, thermal pad layout, and core peripheral mappings - allowing drop-in replacement where memory, security, or peripheral requirements align.
What security features are included in the LPC5502JHI48EL?
The LPC5502JHI48EL includes TrustZone® for memory isolation, PRINCE for real-time flash encryption, HASH-AES for secure boot and data hashing, RNG for entropy generation, Code Watchdog for runtime flow integrity, and RSA-2048/4096 secure boot verification. It lacks CASPER and PUF - features present only in LPC55S0x variants - making it suitable for applications requiring foundational security without asymmetric crypto acceleration.
LPC5502JHI48EL Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 48-VFQFN Exposed Pad
- Series:
- LPC550x
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit Single-Core
- Speed:
- 96MHz
- Connectivity:
- CAN FD, Flexcomm, I2C, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, POR, PWM, RNG, WDT
- Number of I/O:
- 30
- Program Memory Size:
- 64KB (64K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 48K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 7x16b SAR
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount, Wettable Flank
- Supplier Device Package:
LPC5502JHI48EL FAQ
1.How can I place an order for LPC5502JHI48EL through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC5502JHI48EL on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC5502JHI48EL reliable?
The price and inventory of LPC5502JHI48EL are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC5502JHI48EL is usually 5 days.
3.What payment methods are accepted for LPC5502JHI48EL?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC5502JHI48EL transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC5502JHI48EL?
LPC5502JHI48EL orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC5502JHI48EL order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC5502JHI48EL?
For technical support, including LPC5502JHI48EL datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC5502JHI48EL requirements.
6.How does Aetrix verify that LPC5502JHI48EL is sourced from the original manufacturer or authorized distributors?
All LPC5502JHI48EL products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC5502JHI48EL meets industry standards.
7.What is the process for return or replacement of LPC5502JHI48EL?
All LPC5502JHI48EL units undergo pre-shipment inspection (PSI). If there is an issue with LPC5502JHI48EL, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC5502JHI48EL part is unused and in its original packaging.
Return procedure for LPC5502JHI48EL:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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