NXP Semiconductors LPC5502JHI48QL

Overview

LPC5502JHI48QL from NXP Semiconductors is a 32-bit ARM Cortex-M33 microcontroller designed for secure, low-power embedded control applications. It operates at up to 96 MHz, integrates 64 KB flash and 48 KB SRAM, includes CAN 2.0 (not CAN FD), and features a 16-bit 2.0 Msamples/sec ADC with seven analog input channels. It targets industrial sensor nodes and secure IoT edge devices requiring robust power management and cryptographic acceleration.

For engineers reviewing the LPC5502JHI48QL datasheet, LPC5502JHI48QL pinout, LPC5502JHI48QL application, or LPC5502JHI48QL equivalent, key selection criteria include its HVQFN48 package with 30 GPIOs, TrustZone®-enabled security architecture without PUF/CASPER/PRINCE, CAN 2.0 interface, and support for deep power-down wake-up via dedicated pins.

Technical Context

The LPC5502JHI48QL implements ARM Cortex-M33 core r0p4 with FPU, MPU, and TrustZone® for hardware-enforced memory isolation. Its clock system combines internal FRO (96 MHz/12 MHz/1 MHz) and external crystal options (16–32 MHz, 32.768 kHz), enabling precise timing across operating modes.

Digital peripherals include five 32-bit general-purpose timers, one SCTimer/PWM with 10 outputs, a Programmable Logic Unit (PLU), and two DMA controllers (23+10 channels). Analog subsystem comprises a 16-bit ADC (2.0 Msamples/sec, simultaneous dual-channel conversion), comparator, and integrated temperature sensor.

Key Specifications

Pinout & Package

HVQFN48 package: plastic thermal-enhanced very thin quad flat no-lead, 7 mm × 7 mm × 0.85 mm body, exposed pad connected to VSS for thermal and electrical grounding.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microcontroller applications.

Compared with LPC5502JHI48QL, LPC55S02JHI48 adds cryptographic acceleration at identical memory size, while LPC5506JHI48 scales memory capacity without altering security scope or package-enabling direct migration paths for evolving firmware complexity or security requirements.

Availability

LPC5502JHI48QL is available at Aetrix Electronics and suitable for industrial sensor nodes, secure IoT edge gateways, and automotive body control modules requiring stable component supply and long-term lifecycle assurance.

Supply support for LPC5502JHI48QL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets.

The LPC550x series targets cost-optimized, secure embedded control applications where cryptographic acceleration is optional-delivering TrustZone®-enabled safety and CAN 2.0 connectivity in compact HVQFN packages.

FAQ

What is the maximum operating frequency of the LPC5502JHI48QL?

The LPC5502JHI48QL operates at a maximum CPU frequency of 96 MHz. This speed is achieved using the internal Free Running Oscillator (FRO) or external crystal sources, with PLL support for precise clock scaling. The 96 MHz capability enables real-time processing of sensor data and fast response to CAN 2.0 interrupts. All timing specifications in the official NXP datasheet Rev. 1.4 are validated at this frequency under −40 °C to +105 °C conditions. The LPC5502JHI48QL maintains full peripheral functionality-including ADC sampling and SCTimer/PWM-at this rate.

Does the LPC5502JHI48QL support CAN FD or only classical CAN?

The LPC5502JHI48QL supports CAN 2.0 only-not CAN FD. This is confirmed in Table 2 of the NXP datasheet Rev. 1.4, which explicitly lists "CAN2.0" under the LPC5502JHI48 row. Unlike LPC55S0x variants, the LPC5502JHI48QL lacks the CAN FD controller and associated DMA resources. Its CAN module complies with ISO 11898-1:2015 at up to 1 Mbps, with message filtering and FIFO buffering. For designs requiring CAN FD's higher bandwidth or flexible data length, the LPC55S02JHI48 or LPC55S06JHI48 must be selected instead of the LPC5502JHI48QL.

How many analog input channels does the LPC5502JHI48QL ADC support?

The LPC5502JHI48QL integrates a 16-bit ADC with seven analog input channels, as specified in Table 2 of the NXP datasheet Rev. 1.4. These channels are accessible via dedicated pins including PIO0_9/ACMP0_B, PIO0_10/ADC0_1, PIO0_11/ADC0_9, and others listed in the HVQFN48 pinout. The ADC supports simultaneous sampling on differential pairs and achieves 2.0 Msamples/sec throughput. Channel mapping and analog function enablement require proper configuration of the IOCON register's ANAMODE and DIGIMODE bits. The LPC5502JHI48QL's ADC performance is fully characterized across its −40 °C to +105 °C operating range.

What security features are included in the LPC5502JHI48QL?

The LPC5502JHI48QL includes ARM TrustZone® for hardware-enforced memory isolation between secure and non-secure code regions, plus secure boot with RSA-2048/4096 signature verification. However, it omits PUF, CASPER, PRINCE, and HASH-AES modules-confirmed in Table 2 of the NXP datasheet Rev. 1.4 where those columns show "-". It retains Code Watchdog for runtime flow integrity and secure GPIO functionality. Debug authentication is supported via NXP Debug Authentication Protocol v1.0/v1.1. These features make the LPC5502JHI48QL suitable for applications requiring foundational security without advanced cryptographic acceleration. The LPC5502JHI48QL implements all TrustZone®-related registers and NVIC extensions defined for Cortex-M33 r0p4.

What is the package type and pin count of the LPC5502JHI48QL?

The LPC5502JHI48QL uses an HVQFN48 package: a 7 mm × 7 mm × 0.85 mm thermal-enhanced very thin quad flat no-lead package with 48 terminals and an exposed thermal pad connected to VSS. This is confirmed in Table 1 (Ordering Information) and Figure 3 (HVQFN48 pin configuration) of the NXP datasheet Rev. 1.4. The package supports 30 GPIOs, with pin functions including ADC inputs, comparator channels, Flexcomm interfaces, and CAN 2.0 transceiver signals. The exposed pad must be soldered to a PCB thermal plane for optimal thermal performance and electrical grounding. No leaded alternatives (e.g., HTQFP64) are available for the LPC5502JHI48QL variant.