NXP Semiconductors LPC5516JBD100E
- Part No.:
- LPC5516JBD100E
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 100-LQFP Exposed Pad
- Datasheet:
-
LPC5516JBD100E.pdf
- Description:
- IC MCU 32BIT 256KB FLSH 100HLQFP
- Quantity:
- Payment:

- Shipping:

Inventory:107
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC5516JBD100E from NXP Semiconductors is a 32-bit Arm Cortex-M33 microcontroller with TrustZone security, 256 KB flash, 96 KB SRAM, CAN FD interface, USB full-speed and high-speed controllers, and a 16-bit 2.0 Msamples/sec ADC - deployed in secure industrial gateways requiring real-time control and encrypted firmware updates.
For engineers reviewing the LPC5516JBD100E datasheet, LPC5516JBD100E pinout, LPC5516JBD100E application, or LPC5516JBD100E equivalent, key selection factors include its HLQFP100 package, CASPER crypto co-processor support (but no PRINCE or PUF), absence of TrustZone and Secure Boot, and compatibility with Flexcomm serial interfaces for multi-protocol fieldbus bridging.
Technical Context
The LPC5516JBD100E implements an Arm Cortex-M33 core at up to 150 MHz with FPU and MPU but excludes TrustZone and Secure Boot features present in the LPC55S1x series. Its security architecture relies on CASPER for ECC acceleration and HASH-AES for cryptographic operations, without PRINCE flash encryption or PUF-based key generation.
It integrates nine Flexcomm peripherals supporting USART/SPI/I2C/I2S, a dedicated CAN FD controller with DMA, dual DMA engines (23+10 channels), SCTimer/PWM with 10 outputs, and a 16-bit ADC capable of simultaneous differential conversions - all operating across −40 °C to +105 °C with single 1.8–3.6 V supply.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 @ up to 150 MHz with FPU and MPU - enables deterministic real-time control and DSP-intensive sensor fusion. |
| Memory | 256 KB on-chip flash + 96 KB SRAM (16 KB code bus, 64 KB system bus, 16 KB USB SRAM) - supports large firmware images and dual-bank OTA update buffers. |
| Security | CASPER crypto co-processor (ECC acceleration), HASH-AES engine, TRNG, UUID - provides hardware-accelerated asymmetric cryptography without TrustZone isolation or Secure Boot. |
| Connectivity | CAN FD, USB 2.0 full-speed + high-speed (with on-chip PHY), nine Flexcomm interfaces configurable as USART/SPI/I2C/I2S - enables multi-protocol industrial communication with crystal-less FS USB operation. |
| Analog | 16-bit ADC @ 2.0 Msamples/sec with five differential pairs, integrated temperature sensor, comparator - delivers high-resolution, time-synchronized acquisition for motor control and condition monitoring. |
| Timers & Logic | Five 32-bit general-purpose timers, SCTimer/PWM (8 inputs/10 outputs), MRT, RTC, WWDT, PLU - supports complex PWM generation, event-driven state machines, and low-power wake-up scheduling. |
| Package | HLQFP100, 14 × 14 × 0.5 mm, 0.5 mm pitch - provides 64 GPIOs, debug (SWD/JTAG), and thermal performance suitable for convection-cooled industrial PCBs. |
Pinout & Package
HLQFP100 package: 100-pin plastic low-profile quad flat package with exposed thermal pad, 0.5 mm pitch, 14 mm × 14 mm body. Pin 1 marked by corner notch or dot; pin numbering follows counter-clockwise sequence from top-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PIO0_0–PIO0_14, PIO1_0–PIO1_31, PIO2_0–PIO2_15, PIO3_0–PIO3_15 | Multi-function GPIO bank | 64 total GPIOs with configurable pull-up/down, digital filter, and interrupt capability - supports peripheral pin muxing for Flexcomm, CAN, ADC, and secure I/O. |
| VDDA, VSSA, VREFP, VREFN | Analog power & reference | Dedicated 1.8–3.6 V analog supply and precision reference inputs - ensures stable 16-bit ADC performance independent of digital noise. |
| XTAL_IN/XTAL_OUT (12–32 MHz), RTC_XTAL_IN/RTC_XTAL_OUT (32.768 kHz) | Clock sources | Supports external crystals for system clock and RTC - enables accurate timekeeping and jitter-free USB timing without requiring external oscillators. |
| USB_DP/USB_DM (FS), USB_HSDP/USB_HSDM (HS) | USB physical layer | Integrated full-speed and high-speed PHYs - eliminates need for external transceivers and supports crystal-less FS device mode via software library. |
| CAN0_TD/CAN0_RD | CAN FD transceiver interface | Differential transmit/receive pins compliant with ISO 11898-1:2015 - connects directly to external CAN FD transceiver for automotive and industrial networks. |
Key Features
| Feature | Design Value |
|---|---|
| CASPER Crypto Engine | Hardware-accelerated Elliptic Curve Cryptography (ECC) - reduces CPU load during TLS handshake and secure boot verification in resource-constrained edge nodes. |
| Flexcomm Serial Interfaces | Nine software-configurable peripherals (USART/SPI/I2C/I2S) with FIFO and fractional baud-rate generator - enables concurrent RS-485, SPI sensor hub, and I2S audio on shared pins without external logic. |
| SCTimer/PWM | 8-input/10-output state-configurable timer with 16 match/capture registers - implements complex motor control waveforms (e.g., 3-phase BLDC with dead-time insertion) in hardware. |
| 16-bit ADC with Simultaneous Sampling | 2.0 Msamples/sec throughput across two differential channels - captures synchronized current/voltage waveforms for real-time power quality analysis. |
| Programmable Logic Unit (PLU) | Configurable combinatorial/sequential logic with 18 inputs and 18 outputs - replaces discrete glue logic for custom signal routing and safety interlocks without FPGA overhead. |
Applications
| Industrial Gateway | Secure Edge Node |
|---|---|
Use Scenario: Protocol translation between Modbus RTU field devices and MQTT-based cloud infrastructure. IC Role / Device Role / Timing Role: Central MCU managing dual CAN FD buses, USB host for configuration dongles, and Flexcomm UARTs for legacy serial devices. Use Value: 256 KB flash stores multiple protocol stacks; CASPER accelerates TLS 1.2 handshakes; 64 GPIOs route isolated RS-485 transceivers and status LEDs. | Use Scenario: Tamper-resistant sensor aggregator in smart metering with encrypted data logging. IC Role / Device Role / Timing Role: Secure data acquisition unit performing ADC sampling, HMAC-SHA256 signing, and AES-CTR encryption before storage. Use Value: HASH-AES engine signs sensor payloads at line rate; TRNG seeds session keys; 96 KB SRAM buffers encrypted blocks for wear-leveling flash writes. |
| Motor Control Hub | Condition Monitoring Edge Device |
Use Scenario: Compact servo drive controlling PMSM motors with field-oriented control (FOC). IC Role / Device Role / Timing Role: Real-time controller executing FOC loop at 20 kHz using SCTimer-generated PWM and ADC-triggered current sampling. Use Value: 16-bit ADC achieves ±0.1% current measurement accuracy; SCTimer's 10 outputs generate complementary PWM with programmable dead time; PLU enforces hardware safety interlocks. | Use Scenario: Vibration and temperature analytics node on rotating machinery. IC Role / Device Role / Timing Role: Time-synchronized multi-sensor acquisition engine capturing accelerometer, temp, and acoustic data for FFT-based anomaly detection. Use Value: Simultaneous ADC sampling on differential pairs captures phase-aligned vibration spectra; RTC alarm wakes CPU every 100 ms for burst processing; low-power deep-sleep extends battery life to >2 years. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC55S16JBD100 | Includes TrustZone, PRINCE flash encryption, PUF, and Secure Boot - adds hardware root-of-trust not present in LPC5516JBD100E. | Required for certified secure boot in medical or payment systems; unnecessary for basic encrypted firmware updates. | Select when end-product certification (e.g., PSA Level 2, SESIP) mandates hardware-enforced isolation and attestation. |
| LPC5526JBD100 | Same package and core, but adds 1 MB flash, dual-core M33 configuration, and enhanced CAN FD filtering - no TrustZone or Secure Boot. | Better suited for complex real-time OS deployments needing larger code space and task partitioning. | Choose when application firmware exceeds 256 KB or requires asymmetric core utilization (e.g., one core for control, one for comms). |
Compared with LPC55S16JBD100, LPC5516JBD100E omits TrustZone and Secure Boot but retains CASPER and HASH-AES for cost-sensitive secure applications; versus LPC5526JBD100, it offers identical security features at lower flash capacity and single-core simplicity for deterministic control tasks.
Availability
LPC5516JBD100E is available at Aetrix Electronics and suitable for industrial gateways, secure edge nodes, motor control hubs, and condition monitoring devices requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for LPC5516JBD100E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with over 50 years of embedded systems expertise.
The LPC551x series targets cost-optimized, security-aware industrial control applications where hardware crypto acceleration (CASPER/HASH-AES) is required without full TrustZone isolation or certified Secure Boot - balancing performance, security, and bill-of-materials efficiency.
FAQ
Does LPC5516JBD100E support TrustZone security?
No, LPC5516JBD100E does not include Arm TrustZone technology or Secure Boot functionality. These features are exclusive to the LPC55S1x series. The LPC5516JBD100E provides hardware crypto acceleration via CASPER and HASH-AES but relies on software-managed security boundaries. For designs requiring hardware-enforced isolation, the LPC55S16JBD100 is the appropriate alternative part.
What is the maximum ADC sampling rate supported by LPC5516JBD100E?
The LPC5516JBD100E supports a maximum ADC sampling rate of 2.0 Msamples/sec on its 16-bit successive approximation register (SAR) ADC. This rate applies to simultaneous conversions on differential channel pairs, enabling precise time-aligned acquisition for motor current sensing and power quality analysis without external sample-and-hold circuitry.
Can LPC5516JBD100E operate without an external crystal?
Yes, LPC5516JBD100E can operate without an external crystal using its internal Free Running Oscillator (FRO), which delivers 96 MHz (±2% over −40 °C to +105 °C) and 12 MHz outputs. USB full-speed device mode supports crystal-less operation via software library TN00065, though USB high-speed and precise RTC functions require external 32.768 kHz or 12–32 MHz crystals.
How many GPIO pins are available on the LPC5516JBD100E in HLQFP100 package?
The LPC5516JBD100E in HLQFP100 package provides 64 GPIO pins, distributed across four port banks (PIO0–PIO3). All GPIOs support configurable pull-up/down resistors, digital filters, and interrupt generation on rising/falling edges. Eight pins can be configured as pin interrupts (PINT), and two grouped interrupts (GINT) allow logical combinations of input states for efficient event handling.
Does LPC5516JBD100E include PRINCE flash encryption?
No, LPC5516JBD100E does not include the PRINCE real-time flash encryption module. PRINCE is present only in the LPC55S1x series. The LPC5516JBD100E relies on CASPER for asymmetric crypto acceleration and HASH-AES for symmetric operations but lacks on-the-fly encrypted flash storage - making it suitable for applications where firmware confidentiality is managed at the software layer rather than hardware-enforced.
LPC5516JBD100E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 100-LQFP Exposed Pad
- Series:
- LPC551x
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit Single-Core
- Speed:
- 150MHz
- Connectivity:
- CAN FD, Flexcomm, I2C, SPI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, POR, PWM, RNG, WDT
- Number of I/O:
- 64
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 96K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 10x16b SAR
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC5516JBD100E FAQ
1.How can I place an order for LPC5516JBD100E through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC5516JBD100E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC5516JBD100E reliable?
The price and inventory of LPC5516JBD100E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC5516JBD100E is usually 5 days.
3.What payment methods are accepted for LPC5516JBD100E?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC5516JBD100E transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC5516JBD100E?
LPC5516JBD100E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC5516JBD100E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC5516JBD100E?
For technical support, including LPC5516JBD100E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC5516JBD100E requirements.
6.How does Aetrix verify that LPC5516JBD100E is sourced from the original manufacturer or authorized distributors?
All LPC5516JBD100E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC5516JBD100E meets industry standards.
7.What is the process for return or replacement of LPC5516JBD100E?
All LPC5516JBD100E units undergo pre-shipment inspection (PSI). If there is an issue with LPC5516JBD100E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC5516JBD100E part is unused and in its original packaging.
Return procedure for LPC5516JBD100E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC5516JBD100E Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

