My Inquiry
My Account
NXP Semiconductors LPC5516JBD100Y
- Part No.:
- LPC5516JBD100Y
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 100-LQFP Exposed Pad
- Datasheet:
-
LPC5516JBD100Y.pdf
- Description:
- IC MCU 32BIT 256KB FLSH 100LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:963
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC5516JBD100Y from NXP Semiconductors is a 32-bit Arm Cortex-M33 microcontroller with TrustZone security, 256 KB flash, 96 KB SRAM, CAN FD interface, USB full-speed and high-speed controllers, and a 16-bit 2.0 Msamples/sec ADC - deployed in secure industrial gateways requiring real-time control, encrypted firmware updates, and multi-protocol connectivity.
For engineers reviewing the LPC5516JBD100Y datasheet, LPC5516JBD100Y pinout, LPC5516JBD100Y application, or LPC5516JBD100Y equivalent, key selection criteria include HLQFP100 package compatibility, CASPER crypto co-processor support for ECC acceleration, PRINCE-enabled flash encryption, absence of TrustZone and PUF (vs. LPC55S16), and GPIO count (64 pins) for mixed-signal I/O expansion.
Technical Context
The LPC5516JBD100Y implements an Arm Cortex-M33 core at up to 150 MHz with integrated FPU, MPU, and NVIC - but omits TrustZone and PUF hardware per ordering table data. Its security architecture relies on PRINCE-based flash encryption and CASPER for asymmetric cryptography (ECC), while excluding AES-256, SHA2, and secure boot features present in the S-series variants.
It integrates nine Flexcomm interfaces (configurable as USART/SPI/I2C/I2S), dual USB controllers (FS + HS), CAN FD with dedicated DMA, SCTimer/PWM with 10 outputs, five 32-bit general-purpose timers, and a 16-bit ADC with simultaneous differential conversion capability - all operating across −40 °C to +105 °C with single 1.8–3.6 V supply.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 @ up to 150 MHz with FPU and MPU - enables deterministic real-time control and DSP-intensive sensor fusion. |
| Memory | 256 KB on-chip flash + 96 KB SRAM (16 KB code bus + 64 KB system bus + 16 KB USB SRAM) - supports large firmware images and dual-bank OTA updates. |
| Security | PRINCE real-time flash encryption/decryption and CASPER crypto co-processor for ECC acceleration - protects IP without TrustZone or PUF hardware. |
| Connectivity | CAN FD + USB 2.0 full-speed/host-device + USB 2.0 high-speed/host-device - enables automotive-grade diagnostics and high-bandwidth host interfacing. |
| Analog | 16-bit ADC @ 2.0 Msamples/sec with 5 differential/10 single-ended channels and simultaneous conversion - suitable for precision motor current sensing and power quality monitoring. |
| Timers & Logic | SCTimer/PWM (10 outputs, 8 inputs), five 32-bit CTimers, MRT, RTC, WWDT, and PLU - provides flexible PWM generation, time-critical event sequencing, and glue logic replacement. |
| I/O & Package | 64 GPIO pins in HLQFP100 (14 × 14 × 0.5 mm) - delivers high pin density for industrial HMI, sensor aggregation, and protocol bridging applications. |
Pinout & Package
HLQFP100 package: 100-lead plastic low-profile quad flat package, 14 mm × 14 mm body, 0.5 mm pitch, exposed thermal pad, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PIO0_0 to PIO0_14, PIO1_0 to PIO1_31, PIO2_0 to PIO2_31 | Configurable GPIO / peripheral multiplexing | 64 total GPIOs with digital/analog function selection via IOCON registers - supports secure GPIO, pin interrupts (PINT), and grouped interrupts (GINT). |
| VDD, VSS, VBAT, VREFP, VREFN | Power and reference supply | Single 1.8–3.6 V supply operation; separate analog reference inputs enable high-accuracy ADC measurements. |
| XTAL_IN/XTAL_OUT (12–32 MHz), RTC_XTAL_IN/RTC_XTAL_OUT (32.768 kHz) | Crystal oscillator connections | Supports primary system clock and RTC timing with optional bypass mode - critical for time-stamped CAN FD messaging and low-power wake-up. |
| USB_DP/USB_DM (FS), USB_HS_DP/USB_HS_DM | USB physical layer interfaces | Dedicated full-speed and high-speed PHYs with crystal-less FS operation - reduces BOM cost and simplifies USB device enumeration. |
| CAN0_TD/CAN0_RD | CAN FD transceiver interface | Direct connection to external CAN FD transceiver (e.g., TJA1044) - enables 5 Mbps data phase communication in automotive and industrial networks. |
Key Features
| Feature | Design Value |
|---|---|
| CASPER Crypto Engine | Hardware-accelerated Elliptic Curve Cryptography (ECC) for key exchange and digital signatures - offloads CPU during TLS handshake and secure firmware verification. |
| PRINCE Flash Encryption | Real-time AES-128 encryption/decryption of flash reads/writes - enables secure over-the-air updates without exposing decrypted firmware in memory. |
| Flexcomm Interfaces (0–8) | Nine software-configurable serial peripherals supporting USART/SPI/I2C/I2S with FIFOs and fractional baud-rate generators - eliminates need for external protocol bridges in multi-sensor nodes. |
| 16-bit 2.0 Msamples/sec ADC | Simultaneous sampling on differential channel pairs - achieves synchronized current/voltage acquisition for three-phase motor control without external sample-and-hold. |
| Programmable Logic Unit (PLU) | Configurable combinatorial/sequential logic with state machine support - replaces discrete glue logic and enables custom signal conditioning or protocol adaptation in FPGA-like fashion. |
Applications
| Industrial Gateway | Secure Edge Sensor Node |
|---|---|
Use Scenario: Aggregating Modbus RTU, CAN FD, and I2C sensor data for MQTT upload to cloud platforms. IC Role / Device Role / Timing Role: Central protocol translator and secure data concentrator with real-time scheduling and encrypted payload packaging. Use Value: 64 GPIOs and nine Flexcomm interfaces enable concurrent multi-protocol handling; PRINCE ensures firmware integrity during remote updates. | Use Scenario: Battery-powered vibration and temperature monitoring in predictive maintenance systems. IC Role / Device Role / Timing Role: Low-power edge processor performing FFT analysis and anomaly detection before selective data transmission. Use Value: Micro-Tick Timer and RTC wake-up from deep power-down reduce average current to <10 µA; 16-bit ADC captures high-fidelity spectral data. |
| Automotive Diagnostic Tool | Smart Building Controller |
Use Scenario: Handheld OBD-II scanner supporting UDS over CAN FD for ECU reprogramming and live parameter streaming. IC Role / Device Role / Timing Role: High-speed CAN FD interface controller with USB HS host capability for PC tethering and flash programming. Use Value: Dual USB controllers allow simultaneous device-mode (for PC connection) and host-mode (for USB-to-CAN adapter); 150 MHz CPU handles ISO-14229 stack execution. | Use Scenario: HVAC and lighting control unit managing DALI, KNX, and BACnet MS/TP buses in commercial buildings. IC Role / Device Role / Timing Role: Multi-protocol bridge with deterministic timer-driven bus arbitration and secure configuration storage. Use Value: SCTimer/PWM generates precise DALI dimming waveforms; CASPER accelerates certificate-based authentication for BACnet Secure Connect. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC55S16JBD100 | Includes TrustZone, PUF, AES-256, SHA2, secure boot, and RSA-2048/4096 - adds hardware root-of-trust not present in LPC5516JBD100Y. | Required for FIPS 140-2 Level 3 or PSA Certified Level 2 deployments where cryptographic key isolation and attestation are mandatory. | Select when end-product certification mandates hardware-enforced security domains and tamper-resistant key storage. |
| LPC5526JBD100 | Same package and pinout; adds 1 MB flash, 256 KB SRAM, dual-core Cortex-M33, and enhanced CAN FD filtering - no TrustZone or PUF. | Suitable for complex real-time control tasks requiring larger code footprint and parallel processing, such as servo drive firmware with motion profiling. | Choose when application demands higher memory capacity and dual-core determinism without premium security hardware. |
Compared with LPC55S16JBD100, LPC5516JBD100Y trades hardware security extensions for lower cost and power; versus LPC5526JBD100, it offers identical security scope but reduced memory and single-core execution - making it optimal for cost-sensitive, non-certified industrial edge devices.
Availability
LPC5516JBD100Y is available at Aetrix Electronics and suitable for industrial gateways, secure sensor nodes, and automotive diagnostic tools requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for LPC5516JBD100Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The LPC551x series targets cost-optimized, secure embedded control applications where PRINCE-based flash protection and CASPER-accelerated cryptography meet industrial temperature and reliability requirements - without the overhead of full TrustZone implementation.
FAQ
Does LPC5516JBD100Y support TrustZone security?
No, LPC5516JBD100Y does not include Arm TrustZone technology. Per Table 2 in the datasheet, TrustZone is marked "-" for this part number, distinguishing it from the LPC55S1x series. Security relies instead on PRINCE flash encryption and CASPER crypto acceleration. The LPC5516JBD100Y retains the Arm Cortex-M33 core but omits the TrustZone memory isolation hardware block.
What is the maximum ADC sampling rate supported by LPC5516JBD100Y?
The LPC5516JBD100Y supports a maximum ADC sampling rate of 2.0 Msamples/sec for its 16-bit successive approximation register (SAR) ADC. This rate applies to single-channel operation; simultaneous conversions on differential pairs maintain timing coherence without inter-channel skew. The ADC includes five differential input pairs and internal temperature sensor integration.
Can LPC5516JBD100Y execute secure boot functionality?
No, LPC5516JBD100Y does not support secure boot. Table 2 explicitly lists "-" under the Secure Boot column for this part number. While it includes PRINCE for flash encryption and CASPER for ECC operations, it lacks the ROM bootloader features required for cryptographic image validation (e.g., RSA signature verification, x509 certificate parsing, and Root of Trust key storage) found in the LPC55S1x family.
Which packages are available for LPC5516JBD100Y?
LPC5516JBD100Y is offered exclusively in the HLQFP100 package: a 100-lead plastic low-profile quad flat package with 14 mm × 14 mm body and 0.5 mm pitch. This matches the "JBD100" suffix in the part number. Other variants like JEV98 (VFBGA98) and JBD64 (HTQFP64) exist in the LPC5516 family but are distinct orderable parts - LPC5516JBD100Y itself is HLQFP100 only.
Does LPC5516JBD100Y include a Physical Unclonable Function (PUF)?
No, LPC5516JBD100Y does not integrate a Physical Unclonable Function. Table 2 confirms "-" under the PUF Controller column. Unlike the LPC55S1x series, this variant omits the SRAM-based PUF used for silicon fingerprinting and hardware key generation. Key derivation and storage must be implemented externally or via software-managed keys fed into the AES engine.
LPC5516JBD100Y Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 100-LQFP Exposed Pad
- Series:
- LPC551x
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit Single-Core
- Speed:
- 150MHz
- Connectivity:
- CAN FD, Flexcomm, I2C, SPI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, POR, PWM, RNG, WDT
- Number of I/O:
- 64
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 96K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 10x16b SAR
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC5516JBD100Y FAQ
1.How can I place an order for LPC5516JBD100Y through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC5516JBD100Y on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC5516JBD100Y reliable?
The price and inventory of LPC5516JBD100Y are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC5516JBD100Y is usually 5 days.
3.What payment methods are accepted for LPC5516JBD100Y?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC5516JBD100Y transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC5516JBD100Y?
LPC5516JBD100Y orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC5516JBD100Y order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC5516JBD100Y?
For technical support, including LPC5516JBD100Y datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC5516JBD100Y requirements.
6.How does Aetrix verify that LPC5516JBD100Y is sourced from the original manufacturer or authorized distributors?
All LPC5516JBD100Y products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC5516JBD100Y meets industry standards.
7.What is the process for return or replacement of LPC5516JBD100Y?
All LPC5516JBD100Y units undergo pre-shipment inspection (PSI). If there is an issue with LPC5516JBD100Y, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC5516JBD100Y part is unused and in its original packaging.
Return procedure for LPC5516JBD100Y:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC5516JBD100Y Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
