NXP Semiconductors LPC5516JEV98Y
- Part No.:
- LPC5516JEV98Y
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 98-VFBGA
- Datasheet:
-
LPC5516JEV98Y.pdf
- Description:
- IC MCU 32BIT 256KB FLASH 98VFBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LPC5516JEV98Y from NXP Semiconductors is an Arm Cortex-M33 microcontroller with TrustZone security, 256 KB flash, 96 KB SRAM, PRINCE real-time flash encryption, CASPER crypto co-processor, and dual USB (full-speed + high-speed) supporting crystal-less operation - deployed in secure industrial gateways requiring authenticated firmware updates and CAN FD communication.
For engineers reviewing the LPC5516JEV98Y datasheet, LPC5516JEV98Y pinout, LPC5516JEV98Y application, or LPC5516JEV98Y equivalent, key selection criteria include its VFBGA98 package, 64 GPIOs, 16-bit 2.0 Msamples/sec ADC with simultaneous differential conversion, secure boot with RSA-2048/4096, and PUF-based key generation for hardware-rooted identity.
Technical Context
The LPC5516JEV98Y implements Arm TrustZone to isolate secure and non-secure execution environments, with dedicated hardware blocks including PRINCE for on-the-fly encrypted flash access and CASPER for ECC acceleration. Its dual DMA controllers (23-channel DMA0 + 10-channel DMA1) enable concurrent peripheral data movement without CPU intervention.
It integrates nine Flexcomm interfaces - each configurable as USART, SPI, I2C, or I2S - with shared fractional baud-rate generators and FIFOs; the SCTimer/PWM supports 16 capture/match registers and state-machine routing to external pins or internal peripherals, enabling precise timing control in motor control and power conversion.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 @ up to 150 MHz with FPU, MPU, and TrustZone for secure partitioning of code and data. |
| Memory | 256 KB on-chip flash (512-byte page erase/write) + 96 KB SRAM (16 KB code bus, 64 KB system bus, 16 KB USB SRAM). |
| Security | PRINCE flash encryption/decryption, CASPER ECC accelerator, PUF-generated keys (64–4096 bits), SHA2/AES-256, TRNG, and secure boot with x.509 certificate validation. |
| Analog | 16-bit ADC with 2.0 Msamples/sec sampling rate, simultaneous dual-channel differential conversion, integrated temperature sensor, and five-input comparator. |
| Connectivity | CAN FD controller with dedicated DMA, USB 2.0 full-speed + high-speed (on-chip PHY), nine Flexcomm interfaces (USART/SPI/I2C/I2S), and I2C Fast-mode Plus (1 Mbit/s). |
| Timers & Logic | Five 32-bit general-purpose timers, SCTimer/PWM (16 capture/match, 10 outputs), RTC with 1 s resolution, WWDT, PLU for custom logic implementation. |
| Package | VFBGA98 (7 mm × 7 mm × 0.5 mm, 0.5 mm pitch) with 64 GPIOs, operating from −40 °C to +105 °C at 1.8–3.6 V supply. |
Pinout & Package
VFBGA98 package: 98-ball thin fine-pitch BGA, 7 mm × 7 mm body, 0.5 mm ball pitch, compatible with standard reflow profiles and IPC-7351B footprint standards.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PIO0_0 / ACMP0_A | Analog comparator input A or GPIO | Selectable via IOCON register; enables analog sensing only when DIGIMODE=0 and ANAMODE=1 - critical for precision threshold detection in safety-critical monitoring. |
| PIO0_5 / TDI | JTAG test data input or CAN0_TD | Boot source selector at reset; default pull-up enables ISP mode if pulled low - essential for field firmware recovery without debug interface. |
| PIO0_11 / SWDIO | Serial Wire Debug I/O | Default debug interface enabled at reset; supports eight breakpoints and four watchpoints - required for secure development and production programming. |
| USB_DP / USB_DM | USB 2.0 differential data pair | Connected to on-chip FS/HS PHY; crystal-less operation supported in device mode - eliminates external 12 MHz crystal for cost-sensitive USB peripheral designs. |
| VDDA / VSSA | Analog power supply and ground | Dedicated 1.8–3.6 V analog domain with independent filtering - ensures ADC accuracy and comparator stability under digital switching noise. |
Key Features
| Feature | Design Value |
|---|---|
| TrustZone-enabled isolation | Hardware-enforced separation between secure firmware (e.g., bootloader, key storage) and non-secure application code - prevents privilege escalation attacks in OTA update systems. |
| PRINCE flash encryption | Real-time AES-128 encryption/decryption during flash read/write - protects intellectual property and enables secure over-the-air firmware updates without exposing decrypted binaries in memory. |
| CASPER crypto co-processor | Hardware acceleration for Elliptic Curve Cryptography (ECC) operations - reduces signature verification time by >10× vs. software-only implementation, enabling fast TLS handshake in constrained edge nodes. |
| SCTimer/PWM with routing flexibility | 16 capture/match registers and programmable event/state logic - supports complex PWM waveforms (e.g., three-phase motor commutation) with minimal CPU overhead and deterministic latency. |
| Flexcomm serial interfaces | Nine software-configurable peripherals (USART/SPI/I2C/I2S) with shared clock generators and FIFOs - simplifies board design by eliminating discrete level shifters and protocol-specific ICs in multi-interface systems. |
Applications
| Industrial Gateway | Secure Edge Node |
|---|---|
Use Scenario: Aggregating data from CAN FD fieldbus sensors and forwarding to cloud via Ethernet/Wi-Fi using TLS-secured MQTT. IC Role / Device Role / Timing Role: Central MCU managing CAN FD communication, cryptographic signing of telemetry, and real-time scheduling of sensor polling intervals. Use Value: PRINCE-encrypted flash prevents firmware tampering; CASPER accelerates ECDSA signatures; 64 GPIOs support direct sensor interfacing without expansion ICs. |
Use Scenario: Battery-powered smart meter with tamper detection, secure firmware updates, and local energy analytics. IC Role / Device Role / Timing Role: Low-power host executing secure boot, PUF-derived key generation, and RTC-triggered wake-up for periodic measurement bursts. Use Value: Deep power-down mode with RTC wake-up extends battery life; TRNG + SHA2 ensures cryptographically strong challenge-response authentication. |
| Motor Control Module | Medical Diagnostic Interface |
Use Scenario: Closed-loop BLDC motor drive with current sensing, position feedback, and safety monitoring. IC Role / Device Role / Timing Role: Real-time controller coordinating ADC sampling, SCTimer-based PWM generation, and fault response via PLU logic. Use Value: Simultaneous 2.0 Msamples/sec ADC captures phase currents and back-EMF; SCTimer's 16-state machine enables precise commutation sequencing without software jitter. |
Use Scenario: Portable ultrasound probe interface handling analog front-end digitization, beamforming preprocessing, and USB 2.0 HS data streaming to host PC. IC Role / Device Role / Timing Role: High-throughput data mover with DMA-driven ADC transfers, USB HS endpoint management, and CRC-verified packet framing. Use Value: Dual USB controllers (FS + HS) allow debug and data transfer simultaneously; 16-bit ADC meets medical-grade SNR requirements for echo signal fidelity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Arm Cortex-M33 microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC55S16JEV98 | Includes TrustZone, secure boot, PUF, CASPER, and PRINCE - all enabled and factory-configured; identical flash/SRAM/USB/CAN FD specs. | Required where full NXP Secure Boot compliance (TBSA), DICE-compliant device identity, and certified cryptographic acceleration are mandatory. | Select LPC55S16JEV98 when hardware-rooted security certification (e.g., PSA Level 2, SESIP) is required; LPC5516JEV98Y lacks factory-provisioned secure features. |
| LPC5526JEV98 | Same VFBGA98 package, adds second USB HS controller, increases GPIO count to 72, and includes enhanced CAN FD message RAM (up to 128 buffers vs. 64). | Suitable for dual-bus automotive diagnostics tools or redundant communication gateways needing parallel high-bandwidth interfaces. | Choose LPC5526JEV98 when additional USB HS endpoints or larger CAN FD buffer space is needed; otherwise, LPC5516JEV98Y offers optimal cost/performance for single-bus industrial use. |
Compared with LPC55S16JEV98, the LPC5516JEV98Y omits factory-provisioned security features but retains identical peripheral sets and performance - making it suitable for cost-sensitive applications where security is implemented in software or external elements. Versus LPC5526JEV98, it trades extra USB/CAN FD capacity for lower unit cost and simpler BOM.
Availability
LPC5516JEV98Y is available at Aetrix Electronics and suitable for industrial gateways, secure edge nodes, motor control modules, medical diagnostic interfaces, and CAN FD-based telematics systems requiring stable component supply across extended product lifecycles.
Supply support for LPC5516JEV98Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in Arm-based microcontrollers and hardware security IP.
The LPC551x series targets cost-optimized, security-aware embedded applications where robust peripheral integration and long-term supply stability are prioritized over factory-provisioned cryptographic features - distinguishing it from the higher-security LPC55S1x family.
FAQ
What is the maximum operating frequency of the LPC5516JEV98Y?
The LPC5516JEV98Y runs its Arm Cortex-M33 core at up to 150 MHz, supported by PLL0/PLL1 clock synthesis from internal FRO or external oscillators. This frequency is fully validated across the −40 °C to +105 °C temperature range and 1.8–3.6 V supply voltage, enabling deterministic real-time execution in demanding industrial control loops.
Does the LPC5516JEV98Y support secure boot functionality?
The LPC5516JEV98Y includes ROM bootloader support for secure boot, but lacks factory-provisioned secure features like TrustZone configuration, PUF, or CASPER - unlike the LPC55S1x series. It supports RSA-2048/4096 signature verification and x.509 certificate validation, but requires external provisioning of root keys and secure image signing infrastructure.
What are the key differences between LPC5516JEV98Y and LPC55S16JEV98?
The LPC5516JEV98Y shares identical packaging, memory, USB, CAN FD, and analog peripherals with LPC55S16JEV98, but omits factory-provisioned security blocks: no TrustZone-enforced secure world, no PUF, no CASPER crypto accelerator, and no PRINCE flash encryption engine. Its secure boot relies on software-managed keys rather than hardware-rooted trust anchors.
Which development tools are officially supported for LPC5516JEV98Y?
NXP provides MCUXpresso SDK, IDE, and Config Tools for LPC5516JEV98Y, including drivers for all Flexcomm interfaces, SCTimer/PWM, PRINCE (if enabled), and USB stacks. The LPCXpresso55S16 board is hardware-compatible and supports debugging via SWD - though secure feature examples require LPC55S1x silicon.
Can the LPC5516JEV98Y operate without an external crystal?
Yes - the LPC5516JEV98Y integrates multiple internal oscillators: 96 MHz/12 MHz FRO (±2% accuracy), 32 kHz FRO (±2%), and 1 MHz low-power FRO (±15%). Crystal-less USB full-speed device operation is supported using the software library in Technical Note TN00065, eliminating need for external 12 MHz crystal in many applications.
LPC5516JEV98Y Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 98-VFBGA
- Series:
- LPC551x
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit Single-Core
- Speed:
- 150MHz
- Connectivity:
- CAN FD, Flexcomm, I2C, SPI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, POR, PWM, RNG, WDT
- Number of I/O:
- 64
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 96K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 10x16b SAR
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC5516JEV98Y FAQ
1.How can I place an order for LPC5516JEV98Y through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC5516JEV98Y on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC5516JEV98Y reliable?
The price and inventory of LPC5516JEV98Y are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC5516JEV98Y is usually 5 days.
3.What payment methods are accepted for LPC5516JEV98Y?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC5516JEV98Y transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC5516JEV98Y?
LPC5516JEV98Y orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC5516JEV98Y order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC5516JEV98Y?
For technical support, including LPC5516JEV98Y datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC5516JEV98Y requirements.
6.How does Aetrix verify that LPC5516JEV98Y is sourced from the original manufacturer or authorized distributors?
All LPC5516JEV98Y products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC5516JEV98Y meets industry standards.
7.What is the process for return or replacement of LPC5516JEV98Y?
All LPC5516JEV98Y units undergo pre-shipment inspection (PSI). If there is an issue with LPC5516JEV98Y, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC5516JEV98Y part is unused and in its original packaging.
Return procedure for LPC5516JEV98Y:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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