NXP Semiconductors LPC5528JBD100E

Overview

LPC5528JBD100 from NXP Semiconductors is a 32-bit Arm Cortex-M33 microcontroller operating at up to 150 MHz, featuring 512 KB on-chip flash, 256 KB SRAM, and dual USB 2.0 interfaces (full-speed and high-speed) with crystal-less FS operation. It integrates a 16-bit 1.0 Msamples/sec ADC, SCTimer/PWM, PRINCE flash encryption, and SDIO support - deployed in secure industrial gateways requiring real-time control and firmware integrity.

For engineers reviewing the LPC5528JBD100 datasheet, LPC5528JBD100 pinout, LPC5528JBD100 application, or LPC5528JBD100 equivalent, key selection considerations include its HLQFP100 package with 64 GPIOs, absence of CASPER crypto co-processor and PUF compared to LPC55S2x variants, and verified compatibility with NXP's MCUXpresso SDK for secure boot implementation using RSA-2048/4096 signatures.

Technical Context

The LPC5528JBD100 implements an Arm Cortex-M33 core with Memory Protection Unit (MPU), FPU, DSP extensions, and ETM trace support, running at up to 150 MHz from internal FRO or external crystal sources. Its clock system includes dual PLLs, 32 kHz RTC oscillator, and frequency measurement unit for precise timing calibration.

Digital peripherals include two DMA controllers (23+10 channels), nine Flexcomm interfaces configurable as USART/SPI/I2C/I2S, PLU for logic offload, and SCTimer/PWM with 16 capture/match registers and flexible pin routing. Analog subsystem comprises a 16-bit ADC with simultaneous differential conversion capability and integrated temperature sensor.

Key Specifications

Pinout & Package

Package: HLQFP100 - plastic low-profile quad flat package with 100 leads, body size 14 × 14 × 0.5 mm, 0.5 mm pitch (SOT1570-3). Pin functions are software-selectable via IOCON registers; default reset state disables most pull-ups/pull-downs except specific debug and boot pins (e.g., PIO0_5 determines boot source).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microcontroller applications.

Compared with LPC5528JBD100, the LPC55S28JBD100 adds hardware crypto acceleration and PUF for enhanced key lifecycle management, while the LPC5526JBD100 offers identical functionality at lower memory density - both share the same HLQFP100 footprint and pinout, enabling layout reuse across product tiers.

Availability

LPC5528JBD100 is available at Aetrix Electronics and suitable for industrial gateways, secure edge nodes, USB-C host adapters, and low-power HMI controllers requiring stable component supply, long-term manufacturability, and NXP's extended product lifecycle support.

Supply support for LPC5528JBD100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with headquarters in Eindhoven, Netherlands.

The LPC552x series targets cost-optimized secure microcontrollers for industrial and consumer edge devices, delivering robust security primitives (PRINCE, secure boot, UUID) without crypto co-processor overhead - balancing performance, memory, and certification readiness.

FAQ

What is the maximum operating frequency of the LPC5528JBD100?

The LPC5528JBD100 operates at a maximum CPU frequency of 150 MHz, achieved using internal FRO 96 MHz or external crystal/oscillator sources with PLL multiplication. This frequency is sustained across the full industrial temperature range (-40 °C to +105 °C) and 1.8 V to 3.6 V supply voltage, as validated in the Rev. 2.3 datasheet.

Does the LPC5528JBD100 support secure boot, and what cryptographic algorithms does it use?

Yes, the LPC5528JBD100 supports secure boot using RSASSA-PKCS1-v1_5 signature verification of SHA256 digests, with RSA-2048 and RSA-4096 public keys. It validates x509-formatted image keys against up to four revocable Root of Trust keys stored in protected flash, and enforces anti-rollback via serial-number-based image key revocation - all implemented in ROM bootloader.

How many USB interfaces does the LPC5528JBD100 provide, and what are their capabilities?

The LPC5528JBD100 provides two independent USB 2.0 interfaces: one full-speed (FS) and one high-speed (HS), each with dedicated on-chip PHY and DMA controller. The FS interface supports crystal-less operation in device mode using NXP's TN00063 software library, eliminating the need for an external 12 MHz crystal in cost-sensitive designs.

What is the ADC resolution and sampling rate of the LPC5528JBD100?

The LPC5528JBD100 integrates a 16-bit successive-approximation ADC capable of up to 1.0 million samples per second (1.0 Msamples/sec). It supports simultaneous conversions on two channels within a differential pair, with five differential or ten single-ended input channels, and includes an integrated temperature sensor connected directly to the ADC input path.

Is the LPC5528JBD100 pin-compatible with other members of the LPC55S2x/LPC552x family?

Yes, the LPC5528JBD100 in HLQFP100 package is pin-compatible with LPC55S28JBD100 and LPC5526JBD100 in the same package variant. All share identical pin mapping, electrical characteristics, and peripheral signal assignments - enabling hardware reuse across security-tiered and memory-tiered variants without PCB redesign.