NXP Semiconductors LPC5528JBD100Y

Overview

LPC5528JBD100 from NXP Semiconductors is a 32-bit Arm Cortex-M33 microcontroller operating at up to 150 MHz, featuring 512 KB on-chip flash, 256 KB SRAM, dual USB (full-speed + high-speed) with on-chip PHY, and 64 GPIO pins. It integrates a 16-bit 1.0 Msamples/sec ADC, SCTimer/PWM, PRINCE flash encryption, and SDIO interface - deployed in secure industrial gateways requiring real-time control and encrypted firmware updates.

For engineers reviewing the LPC5528JBD100 datasheet, LPC5528JBD100 pinout, LPC5528JBD100 application, or LPC5528JBD100 equivalent, key selection considerations include its HLQFP100 package compatibility, absence of CASPER crypto co-processor and PUF, PRINCE/secure boot omission, and full USB FS+HS support without hardware crypto acceleration.

Technical Context

The LPC5528JBD100 implements an Arm Cortex-M33 core with MPU, FPU, DSP, and ETM, running at up to 150 MHz using PLL0/PLL1 clock sources derived from internal FRO (12 MHz), external crystal (16–32 MHz), or RTC oscillator. It lacks the CASPER co-processor and PUF block present in LPC55S2x variants but retains full USB 2.0 FS+HS controllers with on-chip PHY and crystal-less FS operation capability.

Its memory subsystem includes 512 KB flash with page erase (512 B), 256 KB SRAM (32 KB Code Bus + 208 KB System Bus + 16 KB USB SRAM), and supports PRINCE encryption only in S-series - not enabled in LPC5528JBD100. Security features are limited to SHA2/AES engine, TRNG, UUID, and secure GPIO - excluding RSA, debug authentication, and secure boot chain.

Key Specifications

Pinout & Package

Package: HLQFP100 (SOT1570-3), plastic low-profile quad flat package, 100 leads, body size 14 × 14 × 0.5 mm, 0.5 mm pitch.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microcontroller applications.

Compared with LPC5528JBD100, LPC55S28JBD100 adds hardware crypto acceleration and secure boot enforcement at higher cost and power, while LPC5526JBD100 trades memory capacity for lower unit price - all share identical HLQFP100 pinout and peripheral register mapping.

Availability

LPC5528JBD100 is available at Aetrix Electronics and suitable for industrial gateways, secure edge sensor hubs, USB peripheral bridges, and programmable logic integration nodes requiring stable component supply across extended product lifecycles.

Supply support for LPC5528JBD100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.

The LPC552x series targets cost-optimized, high-performance embedded applications where robust USB connectivity, analog integration, and industrial-grade reliability are prioritized over advanced hardware security blocks.

FAQ

Does LPC5528JBD100 support secure boot?

LPC5528JBD100 includes ROM bootloader support for image integrity checking (CRC32) and flash programming via UART, USB, SPI, or I2C, but it does not implement the full secure boot chain found in LPC55S2x variants. It lacks RSA signature verification, x.509 certificate validation, and Root of Trust key revocation - making it suitable for applications requiring basic firmware protection but not cryptographic attestation. The LPC5528JBD100 relies on SHA2/AES for software-managed encryption rather than hardware-enforced secure boot.

What is the maximum ADC sampling rate for LPC5528JBD100?

The LPC5528JBD100 features a 16-bit successive-approximation ADC capable of up to 1.0 million samples per second (1.0 Msamples/sec). This rate applies to single-channel operation; simultaneous sampling across two channels within the same differential pair is supported at the same aggregate rate. The ADC includes internal reference, multiple trigger sources (timer, software, external), and direct DMA linkage to SRAM - enabling continuous streaming without CPU intervention. This performance is fully retained in the LPC5528JBD100 variant.

Is LPC5528JBD100 pin-compatible with LPC55S28JBD100?

Yes, LPC5528JBD100 is pin-compatible with LPC55S28JBD100 in the HLQFP100 package (SOT1570-3). Both share identical pin count, mechanical footprint, power pin allocation, and peripheral signal mapping - including USB_DP/DM, Flexcomm I/O, ADC inputs, and GPIO. However, certain security-related pins (e.g., PUF key bus, CASPER interface signals) are unused or internally unconnected in LPC5528JBD100. PCB layout designed for LPC55S28JBD100 can be reused for LPC5528JBD100 without modification.

Does LPC5528JBD100 include the CASPER crypto co-processor?

No, LPC5528JBD100 does not include the CASPER crypto co-processor. This hardware accelerator for ECC, RSA, and FFT operations is exclusive to the LPC55S2x family (e.g., LPC55S28JBD100). The LPC5528JBD100 retains the SHA2/AES engine and TRNG but omits CASPER, PUF, and PRINCE modules - resulting in lower power consumption and cost. Applications requiring elliptic curve cryptography must implement algorithms in software or add an external crypto IC when using LPC5528JBD100.

What USB modes does LPC5528JBD100 support?

LPC5528JBD100 supports both USB 2.0 full-speed (12 Mbps) and high-speed (480 Mbps) host and device modes with integrated PHY. Full-speed operation supports crystal-less mode using internal FRO trimming, eliminating the need for an external 12 MHz crystal. High-speed mode requires external termination and proper PCB layout per USB 2.0 HS specifications. The USB controller includes dedicated DMA, endpoint buffers, and HID/CDC/MSD class support via NXP's MCUXpresso SDK - all fully functional in LPC5528JBD100.