NXP Semiconductors LPC5534JBD100MP
- Part No.:
- LPC5534JBD100MP
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 100-LQFP Exposed Pad
- Datasheet:
-
LPC5534JBD100MP.pdf
- Description:
- IC MCU 32BIT 128KB FLSH 100HLQFP
- Quantity:
- Payment:

- Shipping:

Inventory:980
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Product details
Overview
LPC5534JBD100MP from NXP Semiconductors is a 32-bit ARM Cortex-M33 microcontroller for secure embedded control applications, operating at up to 150 MHz with 128 KB on-chip flash, 96 KB SRAM, and integrated CAN FD, USB Full-Speed device/host, FlexSPI with cache, and dual FlexPWM timers for motor control. It targets industrial automation, smart sensors, and connected edge devices requiring real-time responsiveness and low-power operation.
For engineers reviewing the LPC5534JBD100MP datasheet, LPC5534JBD100MP pinout, LPC5534JBD100MP application, or LPC5534JBD100MP equivalent, key selection criteria include its HLQFP100 package with 66 GPIOs, 16-bit 2.0 Msamples/sec ADC with four simultaneous conversions, three 12-bit DACs, and hardware-accelerated PowerQuad DSP engine - all validated for operation from −40 °C to +105 °C.
Technical Context
The LPC5534JBD100MP implements an ARM Cortex-M33 core with TrustZone security, FPU, MPU, and NVIC, paired with a dedicated PowerQuad DSP accelerator using four 4 KB SRAM banks. Its memory subsystem includes 128 KB flash (with 512-byte page erase), 96 KB SRAM (16 KB Code Bus + 80 KB System Bus), and parity/ECC support per bank configuration.
Peripherals are organized around two DMA controllers (52+16 channels), eight Flexcomm interfaces configurable as USART/SPI/I²C/I²S, one I³C bus, CAN FD with dedicated DMA, and dual FlexPWM modules delivering 24 PWM outputs. Clocking relies on trimmable FRO oscillators (96 MHz ±1%, 32 kHz ±2%), PLLs, and crystal options up to 32 MHz.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M33 @ up to 150 MHz with FPU, MPU, TrustZone, and NVIC - enables secure real-time deterministic execution. |
| Memory | 128 KB flash (512-byte page erase) + 96 KB SRAM (16 KB Code Bus + 80 KB System Bus) - supports XIP from FlexSPI and dual-image boot remapping. |
| Analog Peripherals | Four 16-bit 2.0 Msamples/sec ADCs (four simultaneous conversions), three 12-bit 1 Msamples/sec DACs, three OpAmps, four comparators - suitable for sensor signal conditioning and closed-loop control. |
| Connectivity | CAN FD with dedicated DMA, USB 2.0 Full-Speed host/device (crystal-less in device mode), eight Flexcomm interfaces (USART/SPI/I²C/I²S), one I³C - enables robust industrial networking and multi-protocol interfacing. |
| Timers & Control | Five 32-bit general-purpose timers, SCTimer/PWM (16 match/capture registers), MRT, RTC/alarm, WWDT, Micro-tick timer - provides precise timing, PWM generation, and low-power wake-up capability. |
| Package & Environment | HLQFP100 (14 × 14 × 0.5 mm, 100-pin), −40 °C to +105 °C operating range, VDDIO_1: 1.8–3.6 V, VDDIO_2: 1.08–3.6 V - suited for extended-temperature industrial deployments. |
Pinout & Package
HLQFP100 plastic low-profile quad flat package (14 × 14 × 0.5 mm, 100 leads), RoHS-compliant, with exposed thermal pad. Pin functions are software-configurable via IOCON registers; default reset state disables most pull-ups/pull-downs except specific debug and boot pins (PIO0_0, PIO0_2–PIO0_5, PIO0_7, PIO0_9, PIO0_13–PIO0_14).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PIO0_0 / ACMP0_A | GPIO / Analog comparator input A | Configurable digital I/O or ADC/comparator input; enables analog sensing without external signal routing. |
| PIO0_5 / CAN0_TD | GPIO / CAN FD transmit output | Direct CAN FD bus drive capability; boot source selection depends on pin state at reset. |
| PIO0_6 / FLEXSPI0_DATA0 | GPIO / FlexSPI data line 0 | Supports high-speed external flash interface with execute-in-place (XIP) and dual-image remapping. |
| PIO0_7 / HSCMP1_IN0 | GPIO / High-speed comparator input 0 | Enables fast analog threshold detection; boot source selection depends on pin state at reset. |
| PIO0_8 / OPAMP0_INP | GPIO / OpAmp 0 positive input | Direct connection to internal opamp for signal amplification; only OPAMP0 output is routed to pin. |
Key Features
| Feature | Design Value |
|---|---|
| PowerQuad DSP Accelerator | Dedicated hardware engine with four 4 KB SRAM banks for fixed/floating-point math - offloads CPU for real-time audio, motor, or sensor fusion tasks. |
| Flexcomm Interface Flexibility | Eight software-configurable serial peripherals (USART/SPI/I²C/I²S), each with FIFO and fractional baud-rate generator - eliminates need for discrete protocol translators. |
| Secure Boot & Flash Protection | ROM bootloader supporting CRC32 image integrity, dual-image boot, CRP, and OTP eFuse programming - ensures firmware authenticity and anti-tampering in field-deployed systems. |
| Low-Power Operation | Multiple power modes (Sleep, Deep-sleep, Power-down, Deep power-down) with RTC/Micro-tick wake-up sources - extends battery life in edge IoT nodes. |
| Integrated Clocking | Trimmed internal FRO (96 MHz ±1%, 32 kHz ±2%) with PLLs, crystal oscillator support (16–32 MHz), and programmable capacitor banks - reduces BOM cost and board space vs. external crystals. |
Applications
| Industrial Motor Control | Smart Sensor Node |
|---|---|
Use Scenario: Closed-loop control of BLDC/PMSM motors in HVAC actuators or robotic joints. IC Role / Device Role / Timing Role: Main controller executing FOC algorithms via PowerQuad DSP, generating synchronized PWM via dual FlexPWM (24 outputs), and monitoring position via QEI. Use Value: Eliminates external motor control ICs; 150 MHz Cortex-M33 + hardware acceleration achieves <1 µs current loop response time. |
Use Scenario: Multi-sensor environmental monitoring (temp, humidity, gas, vibration) with local analytics and wireless uplink. IC Role / Device Role / Timing Role: Central processing unit acquiring data from 16-channel ADC, running ML inference on PowerQuad, and managing CAN FD/USB communication. Use Value: On-chip 128 KB flash stores firmware + OTA update image; deep-sleep mode draws <2 µA while maintaining RTC alarm wake-up. |
| Automotive Body Electronics | USB-C Accessory Controller |
Use Scenario: Smart junction box managing lighting, window lift, and door lock functions in 12 V vehicle systems. IC Role / Device Role / Timing Role: Safety-aware controller with CAN FD interface, watchdog supervision (WWDT), and temperature monitoring via dual on-die sensors. Use Value: −40 °C to +105 °C rating and brown-out detection (BOD) ensure reliability across automotive ambient conditions. |
Use Scenario: USB-C PD sink controller for portable medical or test equipment requiring host enumeration and firmware updates. IC Role / Device Role / Timing Role: USB Full-Speed device with crystal-less operation (per AN13527), DFU-capable ROM bootloader, and HID-class ISP interface. Use Value: Eliminates external 12 MHz crystal; USB device mode supports field firmware recovery without JTAG debugger. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC5536JBD100MP | 256 KB flash, 128 KB SRAM, same peripheral set - adds 128 KB flash and 32 KB SRAM over LPC5534JBD100MP. | Preferred for complex firmware with OTA updates, larger RTOS images, or dual-application partitioning. | Select when code size exceeds 128 KB or additional RAM is required for buffer-intensive protocols (e.g., USB Audio Class). |
| LPC55S36JHI48/00MP | HVQFN48 package (48-pin), 256 KB flash, no USB FS device/host, no CAN FD - smaller footprint but reduced connectivity. | Suitable for space-constrained consumer devices where CAN FD and USB device functionality are unnecessary. | Choose for compact designs needing lower pin count and cost, but verify USB/CAN FD omission aligns with system architecture. |
Compared with LPC5536JBD100MP, the LPC5534JBD100MP trades flash/SRAM capacity for cost-sensitive industrial control; versus LPC55S36JHI48/00MP, it retains full USB FS and CAN FD in HLQFP100 for wired industrial networks - making it optimal for mid-tier edge nodes balancing performance, I/O, and BOM cost.
Availability
LPC5534JBD100MP is available at Aetrix Electronics and suitable for industrial motor control, smart sensor nodes, automotive body electronics, and USB-C accessory development requiring stable component supply across production lifecycles.
Supply support for LPC5534JBD100MP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with R&D centers across Europe, Asia, and North America.
The LPC553x product line delivers secure, energy-efficient ARM Cortex-M33 microcontrollers optimized for real-time industrial control, sensor fusion, and edge AI - emphasizing hardware-based security, analog integration, and flexible connectivity.
FAQ
What is the maximum operating frequency of the LPC5534JBD100MP?
The LPC5534JBD100MP operates at a maximum CPU frequency of 150 MHz, enabled by its ARM Cortex-M33 core and supported by internal PLLs that can be clocked from the 96 MHz FRO, external crystal (16–32 MHz), or other on-chip oscillators. This frequency is validated across the full −40 °C to +105 °C temperature range and 1.8–3.6 V supply.
Does the LPC5534JBD100MP support crystal-less USB Full-Speed device operation?
Yes, the LPC5534JBD100MP supports crystal-less USB Full-Speed device mode using its internal 96 MHz FRO and software calibration per Application Note AN13527. This eliminates the need for an external 12 MHz crystal in USB device applications, reducing BOM cost and PCB area while maintaining USB compliance.
How many ADC channels and what resolution does the LPC5534JBD100MP provide?
The LPC5534JBD100MP integrates four 16-bit ADCs capable of 2.0 Msamples/sec in 16-bit mode (or 3.2 Msamples/sec in 12-bit mode), supporting up to four simultaneous conversions across independent sequences. It offers 16 single-ended or eight differential input channels, with inputs routed through configurable IOCON registers.
What is the package type and pin count of the LPC5534JBD100MP?
The LPC5534JBD100MP uses the HLQFP100 package: a 100-pin plastic low-profile quad flat package measuring 14 × 14 × 0.5 mm with exposed thermal pad. It provides 66 GPIOs, with pin functions (including Flexcomm, CAN FD, FlexSPI, ADC, and PWM) configurable via IOCON registers.
Does the LPC5534JBD100MP include hardware security features?
Yes, the LPC5534JBD100MP includes ARM TrustZone for Armv8-M, a ROM-based secure bootloader with CRC32 image validation, code read protection (CRP), OTP eFuse programming, and tamper detection pins. These features enable secure boot, firmware authentication, and runtime isolation for sensitive operations.
LPC5534JBD100MP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 100-LQFP Exposed Pad
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit Single-Core
- Speed:
- 150MHz
- Connectivity:
- CAN FD, Flexcomm, I2C, I3C, SPI, UART/USART, USB2.0
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, POR, PWM, WDT
- Number of I/O:
- 66
- Program Memory Size:
- 128KB (128K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 96K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 23x16b; D/A 2x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC5534JBD100MP FAQ
1.How can I place an order for LPC5534JBD100MP through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC5534JBD100MP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC5534JBD100MP reliable?
The price and inventory of LPC5534JBD100MP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC5534JBD100MP is usually 5 days.
3.What payment methods are accepted for LPC5534JBD100MP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC5534JBD100MP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC5534JBD100MP?
LPC5534JBD100MP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC5534JBD100MP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC5534JBD100MP?
For technical support, including LPC5534JBD100MP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC5534JBD100MP requirements.
6.How does Aetrix verify that LPC5534JBD100MP is sourced from the original manufacturer or authorized distributors?
All LPC5534JBD100MP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC5534JBD100MP meets industry standards.
7.What is the process for return or replacement of LPC5534JBD100MP?
All LPC5534JBD100MP units undergo pre-shipment inspection (PSI). If there is an issue with LPC5534JBD100MP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC5534JBD100MP part is unused and in its original packaging.
Return procedure for LPC5534JBD100MP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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