My Inquiry
My Account
NXP Semiconductors LPC5536JHI48/00E
- Part No.:
- LPC5536JHI48/00E
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
LPC5536JHI48/00E.pdf
- Description:
- IC MCU 32BIT 256KB FLASH 48HVQFN
- Quantity:
- Payment:
- Shipping:
Inventory:503
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC5536JHI48/00E from NXP Semiconductors is a 32-bit ARM Cortex-M33 microcontroller operating at up to 150 MHz, featuring 256 KB on-chip flash, 128 KB SRAM, CAN FD interface, and 32 GPIO pins in a 48-pin HVQFN package. It integrates FlexSPI with 8 KB cache, dual FlexPWM timers, three 12-bit DACs, four comparators, and supports industrial motor control and sensor fusion applications.
For engineers reviewing the LPC5536JHI48/00E datasheet, LPC5536JHI48/00E pinout, LPC5536JHI48/00E application, or LPC5536JHI48/00E equivalent, this page delivers verified specifications, validated pin functions, confirmed alternative parts for CAN FD-enabled embedded designs, and real-world use context for low-power industrial edge nodes.
Technical Context
The LPC5536JHI48/00E implements ARMv8-M architecture with TrustZone security, integrated PowerQuad DSP accelerator, and dual DMA controllers (52-channel DMA0 + 16-channel DMA1) enabling concurrent high-bandwidth peripheral access. Its clock system combines FRO (96 MHz ±1%), PLL0/PLL1, and 32.768 kHz RTC oscillator for precise timing across power modes.
Peripherals include eight Flexcomm interfaces configurable as USART/SPI/I²C/I²S, one I³C bus, USB Full-Speed host/device (crystal-less device mode supported), and analog subsystem with 16-bit 2.0 Msamples/sec ADC, three OpAmps (only OPAMP0 output routed to pin), and two QEI modules - all mapped to its 48-pin HVQFN footprint with dedicated VBAT and dual IO supply domains.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M33 @ 150 MHz with FPU, MPU, and TrustZone security |
| Memory | 256 KB flash (246 KB usable), 128 KB SRAM (16 KB code bus + 112 KB system bus) |
| ADC | Four 16-bit channels @ 2.0 Msamples/sec or eight 12-bit @ 3.2 Msamples/sec, supporting four simultaneous conversions |
| DAC | Three 12-bit outputs @ 1.0 MSample/sec, each with independent trigger and buffer control |
| Timers | Five 32-bit general-purpose timers, SCTimer/PWM (16 match/capture registers), RTC with calendar and wake-up from deep power-down |
| Communication | CAN FD with dedicated DMA, USB FS host/device (crystal-less device mode), eight Flexcomm interfaces (USART/SPI/I²C/I²S), I³C, DMIC |
| Package | HVQFN48 (7 × 7 × 0.85 mm), thermal-enhanced, no leads, 32 GPIO pins |
Pinout & Package
HVQFN48 package: 7 mm × 7 mm × 0.85 mm body, thermally enhanced, leadless, 48-terminal layout with exposed thermal pad. Pin 1 marked by dot; pin numbering clockwise from top-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PIO0_0 | GPIO / ACMP0_A input | Digital I/O or comparator A input; default reset state = high-impedance (Z) |
| PIO0_1 | GPIO / ADC1IN2B input | Analog input for ADC1 channel 2B; supports differential pairing with CH2A |
| PIO0_5 | GPIO / CAN0_TD output | CAN FD transmit driver output; boot source selection with PIO0_7 |
| PIO0_7 | GPIO / HSCMP1_IN0 input | High-speed comparator 1 input 0; boot source selection with PIO0_5 |
| PIO0_8 | GPIO / OPAMP0_INP input | OpAmp 0 positive input; only OPAMP0 output is externally accessible |
| VDDA | Analog supply | 1.8–3.6 V analog domain power; decoupling required per datasheet layout guidelines |
| VSSA | Analog ground | Separate analog return path; must be connected to system ground at single point |
| VBAT | Backup supply | 1.71–3.6 V battery backup for RTC and wake logic during main power loss |
Key Features
| Feature | Design Value |
|---|---|
| PowerQuad DSP Accelerator | Hardware-accelerated fixed/floating-point math using four 4 KB SRAM banks; offloads CPU for real-time signal processing |
| FlexSPI with Cache | Octal/QuadSPI interface with 8 KB execute-in-place cache; enables direct XIP from external flash without latency penalty |
| CAN FD with DMA | Dedicated CAN FD controller with hardware timestamping and DMA support; sustains >5 Mbps data phase in automotive diagnostics |
| Crystal-less USB Device Mode | USB Full-Speed device operation without external crystal; uses internal FRO and software library (AN13527) for ±0.25% accuracy |
| Low-Power Wake Sources | RTC (32.768 kHz), Micro-tick Timer (FRO 1 MHz), and GPIO pin interrupts all wake from deep power-down with sub-10 µA retention current |
| Secure Boot & CRP | ROM bootloader with CRC32 image validation, dual-image remap, and Code Read Protection (CRP) for non-secure devices |
Applications
| Industrial Motor Control | Smart Sensor Hub |
|---|---|
Use Scenario: Closed-loop control of BLDC motors in HVAC actuators with real-time torque ripple suppression. IC Role / Device Role / Timing Role: Main controller executing FOC algorithm via PowerQuad, generating 24 PWM outputs via dual FlexPWM, and sampling current/voltage via synchronized ADC sequences. Use Value: 150 MHz M33 core + deterministic SCTimer/PWM ensures <1 µs PWM edge jitter; dual DMA enables concurrent ADC capture and CAN FD telemetry upload. |
Use Scenario: Multi-sensor environmental monitoring node aggregating temperature, pressure, and acoustic data for predictive maintenance. IC Role / Device Role / Timing Role: Central sensor fusion processor interfacing I²C pressure sensors, DMIC array, and analog temperature sensors via shared ADC/DAC resources. Use Value: Integrated DMIC decimators and Voice Activation Detect reduce MCU load; 32.768 kHz RTC enables scheduled ultra-low-power wake cycles every 10 seconds. |
| Automotive Body Electronics | IoT Edge Gateway |
Use Scenario: Door module managing window lift, mirror fold, and interior lighting with LIN/CAN FD gateway functionality. IC Role / Device Role / Timing Role: CAN FD node handling diagnostic requests while running local control logic; Flexcomm interfaces multiplexed as UART (LIN), SPI (EEPROM), and I²C (sensor hub). Use Value: CAN FD's 64-byte payload reduces message count by 4× vs classical CAN; 128 KB SRAM buffers firmware updates during runtime. |
Use Scenario: Secure edge gateway aggregating Zigbee/Z-Wave sensor data and forwarding to cloud via Ethernet/Wi-Fi bridge. IC Role / Device Role / Timing Role: Trusted execution environment (TrustZone) isolates secure boot, OTA update verification, and cryptographic key storage from application firmware. Use Value: Hardware AES engine and OTP eFuse enable secure key provisioning; dual-image remap allows atomic firmware rollback on corruption detection. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC5534JHI48/00E | 128 KB flash, 96 KB SRAM, same 48-pin HVQFN package and peripheral set except no USB FS | Targeted at cost-sensitive CAN FD nodes where USB connectivity is unnecessary | Select when flash/SRAM budget permits reduced memory and USB is unused |
| LPC55S36JHI48/00E | Same memory and peripherals but adds secure boot ROM with cryptographic acceleration (AES/SHA) | Required for applications needing certified secure boot, remote attestation, or encrypted firmware updates | Select when hardware-enforced security compliance (e.g., PSA Level 2) is mandatory |
Compared with LPC5534JHI48/00E, the LPC5536JHI48/00E provides double flash/SRAM and USB FS capability; versus LPC55S36JHI48/00E, it omits cryptographic accelerators but retains identical real-time performance and peripheral feature set for non-secure deployments.
Availability
LPC5536JHI48/00E is available at Aetrix Electronics and suitable for industrial motor control, smart sensor hubs, automotive body electronics, and IoT edge gateways requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for LPC5536JHI48/00E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with over 40 years of microcontroller innovation.
The LPC553x series targets resource-constrained, safety-aware embedded systems requiring real-time determinism, low-power operation, and integrated analog/motor control peripherals - designed specifically for industrial automation and automotive body electronics.
FAQ
What is the maximum operating frequency of the LPC5536JHI48/00E?
The LPC5536JHI48/00E operates at a maximum CPU frequency of 150 MHz using its ARM Cortex-M33 core. This speed is achievable with PLL0 or PLL1 clock sources derived from the internal 96 MHz FRO, external crystal (16–32 MHz), or 32.768 kHz RTC oscillator. The FRO is factory-trimmed to ±1% accuracy across 0°C to 85°C, ensuring stable timing without external components.
Does the LPC5536JHI48/00E support USB Full-Speed device mode without an external crystal?
Yes, the LPC5536JHI48/00E supports crystal-less USB Full-Speed device mode using its internal 96 MHz FRO and software-based clock calibration (documented in Application Note AN13527). This eliminates the need for a 12 MHz crystal, reducing BOM cost and PCB area while maintaining ±0.25% USB timing accuracy required for device enumeration.
How many analog-to-digital converter channels does the LPC5536JHI48/00E provide?
The LPC5536JHI48/00E integrates a 16-bit ADC subsystem with up to eight differential input pairs (or 16 single-ended channels), capable of four simultaneous conversions under dual independent sequence control. In 12-bit mode, it achieves 3.2 Msamples/sec; in 16-bit mode, it delivers 2.0 Msamples/sec - both rates confirmed in the official product data sheet Rev. 5.0.
What is the function of the PowerQuad accelerator in the LPC5536JHI48/00E?
The PowerQuad accelerator in the LPC5536JHI48/00E is a dedicated hardware DSP engine supporting fixed- and floating-point mathematical operations (FFT, FIR, matrix math) using four 4 KB SRAM banks. It operates independently of the CPU, enabling real-time signal processing for motor control, audio analysis, or sensor fusion without compromising M33 core throughput.
Which packages are available for the LPC5536JHI48/00E?
The LPC5536JHI48/00E is exclusively offered in the HVQFN48 package: a 7 mm × 7 mm × 0.85 mm thermally enhanced, leadless quad flat no-lead package with 48 terminals and an exposed thermal pad. This differs from other LPC5536 variants that use HLQFP100 or HTQFP64 packages - the /00E suffix confirms the HVQFN48 variant per NXP's ordering information table.
LPC5536JHI48/00E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 48-VFQFN Exposed Pad
- Series:
- -
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit Single-Core
- Speed:
- 150MHz
- Connectivity:
- CAN FD, Flexcomm, I2C, I3C, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, POR, PWM, WDT
- Number of I/O:
- 32
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 10x16b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC5536JHI48/00E FAQ
1.How can I place an order for LPC5536JHI48/00E through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC5536JHI48/00E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC5536JHI48/00E reliable?
The price and inventory of LPC5536JHI48/00E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC5536JHI48/00E is usually 5 days.
3.What payment methods are accepted for LPC5536JHI48/00E?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC5536JHI48/00E transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC5536JHI48/00E?
LPC5536JHI48/00E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC5536JHI48/00E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC5536JHI48/00E?
For technical support, including LPC5536JHI48/00E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC5536JHI48/00E requirements.
6.How does Aetrix verify that LPC5536JHI48/00E is sourced from the original manufacturer or authorized distributors?
All LPC5536JHI48/00E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC5536JHI48/00E meets industry standards.
7.What is the process for return or replacement of LPC5536JHI48/00E?
All LPC5536JHI48/00E units undergo pre-shipment inspection (PSI). If there is an issue with LPC5536JHI48/00E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC5536JHI48/00E part is unused and in its original packaging.
Return procedure for LPC5536JHI48/00E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC5536JHI48/00E Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
